Measurement of neutron-induced single event transient pulse width narrower than 100ps

Nakamura, Hideyuki; Tanaka, Katsuhiko; Uemura, Tomomasa; Kan, Tetsuo; Fukuda, Toshikazu; Kumashiro, S.

doi:10.1109/irps.2010.5488749

Cited by 12 publications

(4 citation statements)

References 7 publications

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“…the average pulse-width is about 600 ps in [8] which used a chain of 1,000 minimumdrive-strength inverters in 90 nm process. This tendency is consistent with recent results [3], [10]. The pulse-width modulation must be carefully eliminated for SET pulsewidth characterization.…”

Section: Irradiation Experiments and Calibrationsupporting

confidence: 92%

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

Harada

Mitsuyama

Hashimoto

et al. 2014

IEICE Trans. Fundamentals

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This paper presents a measurement circuit structure for capturing SET pulse-width suppressing pulse-width modulation and within-die process variation effects. For mitigating pulse-width modulation while maintaining area efficiency, the proposed circuit uses massively parallelized short inverter chains as a target circuit. Moreover, for each inverter chain on each die, pulse-width calibration is performed. In measurements, narrow SET pulses ranging 5 ps to 215 ps were obtained. We confirm that an overestimation of pulse-width may happen when ignoring die-to-die and within-die variation of the measurement circuit. Our evaluation results thus point out that calibration for within-die variation in addition to die-to-die variation of the measurement circuit is indispensable. key words: soft error, single event transient (SET), pulse-width, pulsewidth modulation, measurement circuit, within-die process variation Ryo Harada (S'09) received the B.E. and M.E. degrees in Information Systems Engineering from Osaka University, Osaka, Japan, in 2009. He is currently pursuing the Ph.D. degree in the Department of Information Systems Engineering at Osaka University. His research interests include soft error estiomation. Yukio Mitsuyama received B.E., M.E., and Ph.D. degrees in Information Systems Engineering from Osaka University, Japan, in 1998, 2000, and 2010, respectively. He is currently an Associate Professor in School of Engineering, Kochi University of Technology. His research interests include reconfigurable architecture and its VLSI design. He is a member of IEEE and IPSJ. sity. His research interest includes computeraided design for digital integrated circuits, and high speed and low power circuit design. Dr. Hashimoto served on the technical program committees for international conferences including DAC, ICCAD, ITC, Symposium on VLSI Circuits, ASP-DAC, DATE, and ISPD. He is a member of IEEE, ACM and IPSJ. Takao Onoye received the B.E. and M.E. degrees in Electronic Engineering, and Dr.Eng. degree in Information Systems Engineering all from Osaka University, Japan, in 1991Japan, in , 1993Japan, in , and 1997. He is currently a professor in the Department of Information Systems Engineering, Osaka University. His research interests include media-centric low-power architecture and its SoC implementation. He is a member of IEEE, IPSJ, and ITE-J.

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Section: Irradiation Experiments and Calibrationsupporting

confidence: 92%

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

Harada

Mitsuyama

Hashimoto

et al. 2014

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

show abstract

“…the average pulse-width is about 600 ps in [7] which used a chain of 1,000 minimum-drive-strength inverters in 90 nm process. This tendency is consistent with recent results [3,8]. The pulse-width modulation must be carefully eliminated for SET pulse-width characterization.…”

Section: Radiation Experiments and Calibrationsupporting

confidence: 92%

SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

Harada

Mitsuyama

Hashimoto

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Abstract-This paper presents a measurement circuit structure for capturing SET pulse-width suppressing pulse-width modulation and within-die process variation effects. For mitigating pulse-width modulation while maintaining area efficiency, the proposed circuit uses massively parallelized short inverter chains as a target circuit. Moreover, for each inverter chain on each die, pulse-width calibration is performed. In measurements, narrow SET pulses ranging 5 ps to 215 ps were obtained. We confirm that an overestimation of pulse-width may happen when ignoring die-to-die and within-die variation of the measurement circuit. Our evaluation results thus point out that calibration for within-die variation in addition to die-to-die variation of the measurement circuit is indispensable.

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“…Chain length dependence -comparison with the previous work Fig. 6 shows target chain length dependence of SET pulse width distribution of 90nm INV x1 cell, which has been reported in [10]. Fig.7 is 40nm data for comparison with 90nm data in Fig.6.…”

Section: Resultsmentioning

confidence: 61%

“…For evaluating the SET impacts on actual logic LSIs, chain length of about 20 stages is appropriate on the SET target because the number of stages is similar to actual logic circuits. We have suggested SET measurement circuit with using the short chain targets and a compact pulse measurement circuit [10]. In the measurement, it is clarified that the most of the pulse widths of neutron induced SET are shorter than 100ps in 90nm measurement.…”

Section: Introductionmentioning

confidence: 99%

Scaling effect and circuit type dependence of neutron induced single event transient

Nakamura

Uemura

Kan

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Neutron induced single event transient (SET) has been measured on NAND and inverter (INV) chain with changing fanout, drive strength, size of drain diffusion area, temperature and VDD on 40nm and 90nm bulk CMOS technology. As the pulse width distribution varies with the length of SET target chain as well, it is important to use the chain length similar with the actual logic circuits. Using tens of stages of target chain, pulses wider than 150ps have been rarely observed. The results of the measurement show that the SER of SET changes depending on the cell type and fan-out. SER of SET in combinational logic circuits decreases by half from 90nm to 40nm for the same gate count and the same clock frequency.

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Measurement of neutron-induced single event transient pulse width narrower than 100ps

Cited by 12 publications

References 7 publications

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

Scaling effect and circuit type dependence of neutron induced single event transient

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