McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems

Guler, Abdullah; Jha, Niraj K.

doi:10.1109/tvlsi.2020.3002723

Cited by 13 publications

(3 citation statements)

References 34 publications

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“…Based on high-level data, such as the frequency of operation of the core, McPAT can predict the architectural level power usage of the processor core containing caches and memory controllers. A McPAT-monolithic framework is presented in [25] for the architecture modeling of 3-D hybrid monolithic multi-core systems. The work in [26] proposes a microarchitectural framework to estimate the performance and energy consumption of cores in a multi-core processor.…”

Section: Literature Reviewmentioning

confidence: 99%

Machine Learning based Electromigration-aware Scheduler for Multi-core Processors

P¹,

Mini²

2022

IJACSA

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The rising performance demands in modern technology devices see the need to pack more functionality per area and are made possible with the advent of technology scaling. The extremely down-scaled, high-density processors used in such technology devices functioning at high frequencies and greater temperatures expedite various aging effects which impact the reliable lifetime of computing systems. Electromigration is considered to be an important intrinsic aging effect that reduces the useful lifetime of modern microprocessors. The objective of this work is to use machine learning methods to develop an electromigration-aware scheduler for assigning workloads to cores based on reliability and performance requirements. Aging estimation of the processor cores is performed based on the proposed computationally efficient and accurate regressionbased thermal prediction models. According to experimental findings, the suggested technique can significantly extend the lifetime of multi-core architectures while allowing performance to degrade gracefully. The maximum error in the prediction of the lifetime of the cores using the proposed methodology is estimated to be 2.85%.

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Section: Literature Reviewmentioning

confidence: 99%

Machine Learning based Electromigration-aware Scheduler for Multi-core Processors

P¹,

Mini²

2022

IJACSA

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“…These lines are given vertically or horizontally, and the modules are dumped in a rectangle form to improve the automation process. The elimination of the module in floor planning is indeed a significant issue (Guler and Jha 2020;Sari and Psarakis 2017;Kouchi et al 2020;Guo et al 2018;Choudhury and Pradhan 2019). Typically, there are 2 types of floor plans: (1) Slicing the floor plan, i.e.…”

Section: Introductionmentioning

confidence: 99%

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

Pondreti

Kaparapu

2023

International Journal of Swarm Intelligence Research

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Floor planning is indeed an obvious design process in VLSI physical layout since it specifies the dimensions, structure, as well as positions of components upon the chip; in addition, information regarding the overarching silicon area, interlinks, and latency is also provided. VLSI floor planning is an NP-hard issue as the floor plan representations are a crucial component in this process. The intricacy, as well as solution space of the floor plan layout, is influenced by the floorplan visualizations. To tackle the VLSI floor plan challenge, numerous researchers have developed numerous meta-heuristic optimization techniques. The main objective of this work presents a novel multi-objective hybrid optimization method for solving the floor plan optimization issue. Standard DOX and ALO are conceptually combined in the proposed hybrid optimization referred to as Dingo Updated Ant Lion Optimization (DUALO) model. The multi-objectives like wire length, area, and penalty function are taken into consideration.

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“…In order to address with these issues, monolithic three-dimensional (M3D) IC, which possesses excellent performance and power efficiency, has been proposed and is now rapidly developing [3]. M3D ICs are implemented in silicon-on-insulator (SOI) technology, and through-oxide vias (TOV) are patterned through the buried oxide (BOX) to offer electrical connectivity between tiers [4,5].…”

Section: Introductionmentioning

confidence: 99%

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

et al. 2021

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In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the substrate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 μA, sub-threshold swing of 69 mV/dec, and on/off current ratio of 1.28 × 1011. Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the influence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications.

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McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems

Cited by 13 publications

References 34 publications

Machine Learning based Electromigration-aware Scheduler for Multi-core Processors

Machine Learning based Electromigration-aware Scheduler for Multi-core Processors

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

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