2018
DOI: 10.1007/978-3-030-01090-4_27
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Maximum Realizability for Linear Temporal Logic Specifications

Abstract: Automatic synthesis from linear temporal logic (LTL) specifications is widely used in robotic motion planning, control of autonomous systems, and load distribution in power networks. A common specification pattern in such applications consists of an LTL formula describing the requirements on the behaviour of the system, together with a set of additional desirable properties. We study the synthesis problem in settings where the overall specification is unrealizable, more precisely, when some of the desirable pr… Show more

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Cited by 18 publications
(19 citation statements)
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“…After we determine which rules (i.e., S r (t)) need to be relaxed through the receding horizon approach introduced above, we apply the control from solving (20) with k = 0 only one time step forward at the current time. This is due to the fact that the state estimation errors of the instances and the error of the predictive model (18) with respect to (1) increases as k increases.…”
Section: Online Optimal Controlmentioning
confidence: 99%
“…After we determine which rules (i.e., S r (t)) need to be relaxed through the receding horizon approach introduced above, we apply the control from solving (20) with k = 0 only one time step forward at the current time. This is due to the fact that the state estimation errors of the instances and the error of the predictive model (18) with respect to (1) increases as k increases.…”
Section: Online Optimal Controlmentioning
confidence: 99%
“…max-realizability. These are a set of instances involving the synthesis of systems satisfying a collection of linear temporal logic (LTL) formulas (specifications) [12]. If the synthesized system satisfies one of the LTL formulas f , then f is said to be realized.…”
Section: Submitted Benchmarksmentioning
confidence: 99%
“…Thus, we conclude that T |= ψ v . Clearly, ψ v also satisfies condition (1). Now, consider a transition system T with T |= ψ v .…”
Section: Bounded Maximum Realizabilitymentioning
confidence: 99%
“…We implemented the proposed approach to maximum realizability 1 Each experiment was run on a machine with a 2.3 GHz Intel Xeon E5-2686 v4 processor and 16 GiB of memory. While the processor is quad-core, only a single core was used.…”
Section: Experimental Evaluationmentioning
confidence: 99%
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