Mathematical Modeling of Memristors

Oğuz, Yasin

doi:10.5772/intechopen.73921

Cited by 8 publications

(12 citation statements)

References 17 publications

(38 reference statements)

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“…A minimum voltage drop at during RESET operation is required [18]. For Xbar PUF 1 , the optimum load resistance , comes out to be 0.35MΩ, 0.176MΩ, 88.39kΩ and 44.19kΩ for N = (16,32,64,128) respectively. It is seen that as the Xbar size is increased, the value of , tends to decrease from MΩ to kΩ.…”

Section: Resultsmentioning

confidence: 99%

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Optimization of Memristive Crossbar Array for Physical Unclonable Function Applications

et al. 2021

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The memristive crossbar Physical Unclonable Function (PUF) structures are emerging as strong security primitives for resource-constrained devices demanding good retention time, negligible standby power, small size, and ultra-low power operating requirements. Memristive PUFs exploit the inherent high process variations of a memristor as a source of entropy to generate device-specific signatures. These PUFs need to be strong enough to deal with active and passive attacks as well as machine learning attacks. This requires more variability in the device characteristics. Memristive PUF requires dense crossbar architecture to generate unique, uniform, and reliable device signatures. Dense memristive crossbars (Xbar) face the challenge of low noise margin, proper load resistance selection, scalability, and a precise sense circuitry at the load resistance side to read the resistive states of a memristor accurately. In this work, we have simulated and optimized the load resistance of memristive scaled up crossbar arrays. We have used two of our fabricated devices for memristive crossbar PUF simulation. The proposed crossbar PUF architecture satisfies the basic PUF evaluation metrics and improves noise margin (NM). The load resistance is optimized through MATLAB simulation. The impact of optimized load resistance on Xbar architecture is observed to be noticeable and around 18% improvement in the noise margin was observed when the crossbar is scaled up from 16×2 to 128×2.

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Section: Resultsmentioning

confidence: 99%

“…A RESET operation refers to change of memristive state from LRS to HRS, while SET is the transition from HRS to LRS. The memristance of a memristor [32] is written as…”

Section: Figure 1 Hp Memristor Modelmentioning

confidence: 99%

Optimization of Memristive Crossbar Array for Physical Unclonable Function Applications

et al. 2021

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“…There are several memristor model have been discovered in the [12], [13], [14] and [15]. In this paper, we will highlight four of the models which associated and related to this study.…”

Section: Recent Memristor Technologymentioning

confidence: 95%

“…TEAM [12] model switching mechanism is based on current. For this model, the status variable is not change for current below a certain threshold value.…”

Section: Threshold Adaptive Memristor (Team) Modelmentioning

confidence: 99%

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Simulation Study of Memristor-Based Digital Logic Circuit using Stateful Logic

Hamid¹

2020

IJETER

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Computer technology consists of three basic block of logic gate, which is NOT, AND, and OR gate. When apply memristor into logic gate, a new logic operation needs to be introduced, called material implication, IMPLY. This study is an attempt to investigate performance of memristor using LT SPICE model with Boilek and Prodromakis window function. We incorporate the SPICE model of memristor to simulate the IMPLY stateful logic circuit. As a result, Biolek memristor switching performance is 35ms faster than Prodromakis memristor at 1.2V while both recorded highest percentage of correct output at 4Hz with similar time taken of 1s. As a conclusion, both Biolek and Pedromakis windows function simulation and transient analysis showed the characteristics of the memristor, but the current step size remained a constraint for further performance review.

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