Mathematical Model for Multiobjective Synthesis of NoC Architectures

Abdallah, Abderazek Ben; Akanda, Md. Musfiquzzaman; Yoshinaga, Tsutomu; Sowa, Masahiro

doi:10.1109/icppw.2007.50

Cited by 4 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Alabei (2010) has proposed a custom NoC synthesis procedure that uses B*-tree for floorplan representation. A multiobjective mathematical model for NoC synthesis has been suggested in Abderazek et al (2007). A custom NoC instantiation tool Xpipes Compiler was presented by Jalabert et al (2004), which is based on the inputs as specified by the designer.…”

Section: Literature Surveymentioning

confidence: 99%

Network-on-Chip

Kundu¹,

Chattopadhyay²

2018

View full text Add to dashboard Cite

This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint.The Open Access version of this book, available at www.taylorfrancis.com, has been made available under a Creative Commons Attribution-Non Commercial-No Derivatives 4.0 license.

show abstract

Section: Literature Surveymentioning

confidence: 99%

Network-on-Chip

Kundu¹,

Chattopadhyay²

2018

View full text Add to dashboard Cite

show abstract

“…RELATED WORKS In the work [9], the authors presented a mathematical model for NoC based system high-level synthesis (IP placement).…”

Section: Introductionmentioning

confidence: 99%

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

Ying

Hollstein

2012

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

View full text Add to dashboard Cite

3D ICs have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoC). Along with the advantages, it also imposes lots of challenges in terms of cost efficiency, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoC) is thoroughly investigated in 2D SoC design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D for any application should be justified by the improvements in performance, power, latency and the utilization of Through-Silicon-Via (TSV). In this paper, we present a communication-centric metric for high level 3D NoCs synthesis, which can be used to improve the system performance and to reduce the link heat degree significantly by distributing the communication evenly in the system. We take several state-of-the-art benchmarks and the generic scalable pseudo application (GSPA) with different network sizes for experiments, by combining the simulated annealing algorithm with the presented metric. In comparison to the well-know metrics (dynamic communication energy aware and contention count), our metric can generally maintain the system performance and achieve up to 48% advantage on the aspect of Hottest Link Degree. All the experiments have been done in SystemC-RTL, which can achieve the cycle accuracy.

show abstract

Application-Specific Network-on-Chip Synthesis

Kundu¹,

Chattopadhyay²

2018

Network-on-Chip

View full text Add to dashboard Cite

Mathematical Model for Multiobjective Synthesis of NoC Architectures

Cited by 4 publications

References 11 publications

Network-on-Chip

Network-on-Chip

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

Application-Specific Network-on-Chip Synthesis

Contact Info

Product

Resources

About