Mathematical Analysis and Experiment Validation of Modular Multilevel Converters

Abstract

This paper describes operating and capacitor voltage balancing of the modular multilevel converter. The paper focuses on sizing of the cell capacitor and establishes approximate expressions for the capacitor voltage. Simulations and experiments results obtained from three-level modular converter are used to demonstrate its viability in medium voltage applications. It is shown that the modular converter can operate over the full modulation index linear range independent of load power factor.

A Simple Capacitor Voltage Balancing Method with a Fundamental Sorting Frequency for Modular Multilevel Converters

“…It can be seen that the maximum value of the maximum ripple of the capacitor voltage occurs when the load is a resistive-inductive or a resistive-capacitive load, not a pure resistor, inductor or capacitor. When the load impedance angle is (19), the maximum ripple of the DC bias obtains its maximum value (20). When the load is a pure resistive load, the maximum ripple of the DC bias acquires its minimum value πm V /4.…”

“…When compared with diode or flying capacitor clamped multilevel converters, the MMC has many merits such as modular construction, redundancy, low switching frequency, low losses and low harmonics [1]- [3]. From recent publications, MMC-related studies are mainly focused on modulation strategies [3]- [8], modeling [9], [10], theoretical calculations [11], [12] and capacitor voltage balancing methods [4], [5], [13]- [17]. The capacitor voltage balancing method is critical for MMCs, as it is related to the safe operation of the whole system and has a significant impact on the output waveform.…”

Experimental Validation of a Cascaded Single Phase H-Bridge Inverter with a Simplified Switching Algorithm

“…R 1 , R 2 , R 3 , R 4 and R 5 whereas the number of auxiliary switches in the 23 Level inverter will be four. As per the algorithm, the permutation P1 will be:…”

“…The first and last columns of the above P 1 will be responsible for constructing the switching patterns for AS 1 and AS 4 , and the 2nd and 3rd columns are used for developing the switching pattern for AS 2 and AS 3 . Columns 2 and 3 have only three unique R signals (i.e.)…”

“…Circuit proposed in the [36] Proposed Cascaded (3) is a simple zero crossing detector, while (4) gives the expected output of the lower H-bridge inverter (Vlow) and (5) is a mathematical representation of the upper H-bridge inverter reference waveform. The output of equations (4) and (5) for the 11 level inverter are shown in Fig.…”