MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture

Sakthivel, Erulappan; Veeraraghavan, Malathi; Arunraja, Muruganantham

doi:10.1016/j.micpro.2014.06.001

Cited by 9 publications

(21 citation statements)

References 26 publications

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“…In the first stage of the work, suitable SA is selected with respect to the power comparison in both sleep and active mode [8] (observed M-DTSA, MCG-DTSA for further process). After clock enable [9], both DTSA's refined into B-DTSA and BCG-DTSA.…”

Section: Proposed Systemmentioning

confidence: 99%

“…In the third stage, we designed the V-DTSA circuitry for complete transceiver. Finally, we compared our results with [7] [8]. The block diagram of VELAN design is shown in Figure 2.…”

Section: Proposed Systemmentioning

confidence: 99%

“…This DTSA with transceiver consists of PEC at the transmitter and DTSA at RXS [7]. In a recent paper [8], we presented transceiver with Reconfigurable DTSA (R-DTSA) to achieve the performance improvement. Both [7] and [8] has achieved a reduction in data rate and link power.…”

Section: Introductionmentioning

confidence: 99%

“…In a recent paper [8], we presented transceiver with Reconfigurable DTSA (R-DTSA) to achieve the performance improvement. Both [7] and [8] has achieved a reduction in data rate and link power. In this paper, we have concentrated on improving the latency parameter by adapting the bootable concept in DTSA.…”

Section: Introductionmentioning

confidence: 99%

“…The traffic estimator and generator are introduced for QoS in [14], to generate and estimate the real time traffic data in on-chip communication. In this proposed VELAN design, we followed the Traffic generator [8] and Graph Theory based Traffic Estimator (GTE) [8]. To achieve higher performance under various traffic conditions in on-chip networks, energy recovery clocking [15] concept is introduced in DTSA called M-DTSA [8] and clock gating [13] concept in M-DTSA [8] called MCG-DTSA [8].…”

Section: Introductionmentioning

confidence: 99%

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VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

2016

Self Cite

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A real time multiprocessor chip paradigm is also called a Network-on-Chip (NoC) which offers a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy and latency than its intended design during heavy traffic condition. Variable Energy aware sense amplifier Link for Asynchronous NoC (VELAN) is designed in this research to eliminate the difficulty, which is the combination of Variable DTSA circuitry (V-DTSA) and Transceiver. The V-DTSA circuitry has following components such as bootable DTSA (B-DTSA) and bootable clock gating DTSA (BCG-DTSA), Graph theory based Traffic Estimator (GTE) and controller. Depending upon the traffic rate, the controller activates necessary DTSA modules and transfers information to the receiver. The proposed VELAN design is evaluated on TSMC 90 nm technology, showing 6.157 Gb/s data rate, 0.27 w total link power and 354 ps latency for single stage operation.

show abstract

Section: Proposed Systemmentioning

confidence: 99%

“…In the third stage, we designed the V-DTSA circuitry for complete transceiver. Finally, we compared our results with [7] [8]. The block diagram of VELAN design is shown in Figure 2.…”

Section: Proposed Systemmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

2016

Self Cite

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An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System

Mariyappan¹,

Veeraraghavan²,

Ramachandradurai

2020

Arab J Sci Eng

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Design of optimised logic interface for network‐on‐chip architectures

Sakthivel¹,

Arunraja²,

Uma³

et al. 2018

Electron. lett.

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Achievement of low power consumption in the field of networkon-chip (NoC) is a prominent research in recent days. Many works have attempted to improve performance in NoC using architectural and algorithmic models. The researches attempted to mitigate certain factors like power consumption, speed, complexity, scalability, and flexibility. Currently, NoC engineers incorporated external or internal sense amplifier (SA) in the architectural model of NoC. In the conventional double-tail SAs (DTSAs), more amount of energy is consumed in the heavy traffic state. Hence, many improved DTSAs like reconfigurable DTSA (R-DTSA), variable energy aware SA link for asynchronous NoC (VELAN) DTSA (V-DTSA) were proposed in the previous works and employed with the transceivers. They were evaluated on TSMC 90 nm technology with the real-time data traffics which are obtained using traffic estimators and traffic generators. An optimised logic interface for transceivers of NoC which is superior to the conventional DTSA, R-DTSA, and V-DTSA is developed. The proposed design is implemented with transceivers and evaluated on TSMC 90 nm technology for comparing the performance with the previous SAs.

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MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture

Cited by 9 publications

References 26 publications

VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System

Design of optimised logic interface for network‐on‐chip architectures

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