Material and electrical characterization of TMS-based silicidation of the Cu-dielectric barrier interface for electromigration improvement of 65nm interconnects

Plantier, L.; Friec, Y. Le; Humbert, A.; Imbert, G.; Sabouret, E.; Sardo, M.; Girault, V.; Delille, D.; Jullian, S.; Junker, K.

doi:10.1016/j.mee.2006.10.046

Cited by 7 publications

(4 citation statements)

References 9 publications

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“…Many of the reported methods involve either doping the Cu lines with a few percent of select alloying elements, [376][377][378][379][380][381][382] or selectively forming an additional surface passivation layer material between the DB and Cu. [383][384][385][386][387][388][389][390][391][392][393] In most cases, these methods involve additional processing steps separate from the DB deposition process. However, one method that has been integrated with the DB deposition involves selectively forming a CuSiN interfacial layer between the DB and Cu.…”

Section: N3037mentioning

confidence: 99%

“…However, one method that has been integrated with the DB deposition involves selectively forming a CuSiN interfacial layer between the DB and Cu. [383][384][385][386][387][388][389][390][391] This is achieved in-situ prior to DB deposition by pre-exposing the post Cu CMP interconnect surface to SiH 4 which selectively and catalytically decomposes on the Cu line to form a CuSi x surface layer. This surface layer is then converted into CuSiN by performing a nitridizing plasma treatment that is then followed by the DB deposition.…”

Section: N3037mentioning

confidence: 99%

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Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

132

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: N3037mentioning

confidence: 99%

Section: N3037mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

132

115

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“…Zink based oxide semiconductors with high mobility must decrease the resistivity and mismatching at the interface between a channel and dielectric material [4][5][6][7][8][9]. Also, the understanding that a contact mechanism at the interface in a device is also an important factor.…”

Section: Introductionmentioning

confidence: 99%

Correlation between the Annealing Effect and the Electrical Characteristics of the Depletion Region in ZnO, SnO₂and ZTO Films

Oh¹

2016

Transactions on Electrical and Electronic Materials

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To research the correlation between oxygen vacancy and the electrical characteristics of ZTO, which is made by using a target mixed ZnO:SnO 2 =1:1, the ZnO, SnO 2 and ZTO were analyzed by PL, XPS, XRD patterns and electrical properties. It was compared with the electron orbital spectra of O 1s in accordance with the electrical characteristics of ZnO, SnO 2 and ZTO. The electrical characteristics of ZTO were improved by increasing the annealing temperatures, due to the high degree of crystal structures at a high temperature, and the physical properties of ZTO was similar to that of ZnO. The amorphous structure of SnO 2 was increased with increasing the temperature. The Schottky contact of oxide semiconductors was formed using the depletion region, which is increased by the electron-hole combination due to the annealing processes. ZnO showed the Ohmic contact in spite of a high annealing temperature, but SnO 2 and ZTO had Schottky contact. As such, it was confirmed that the electrical properties of ZTO are affected by the molecules of SnO 2 .

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“…Recently, attention has been focused on the zink based oxide (ZnO) semiconductors due to their superior characteristics that include a flexibility and transparency for application to electronic devices [1][2][3][4][5][6]. One promising candidate material for electronic device oxide semiconductors is a zink tin oxide (ZTO), made by mixing of ZnO : SnO 2 =1 : 1.…”

Section: Introductionmentioning

confidence: 99%

A Study on an Oxygen Vacancy and Conductivity of Oxide Thin Films Deposited by RF Magnetron Sputtering and Annealed in a Vacuum

Oh¹

2017

Transactions on Electrical and Electronic Materials

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Usually, the oxygen vacancy is an important factor in an oxide semiconductor device because the conductivity is related to the oxygen vacancy, which is formed at the interface between oxide semiconductors and electrodes with an annealing processes. ZTO is made by mixing n-type ZnO and p-type SnO 2 . Zink tin oxide (ZTO), zink oxide (ZnO) and tin oxide (SnO 2 ) thin films deposited by RF magnetron sputtering and annealed, to generate the oxygen vacancy, were analyzed by XPS spectra. The contents of oxygen vacancy were the highest in ZTO annealed at 150 o C℃ , ZnO annealed at 200 o C and SnO 2 annealed at 100 o C. The current was also increased with increasing the oxygen vacancy ions. The highest content of ZTO oxygen vacancies was obtained when annealed at 150 ℃ . This is the middle level in compared with those of ZnO annealed at 200 o C and SnO 2 annealed at 100 o C℃ . The electrical properties of ZTO followed those of SnO 2 , which acts a an enhancer in the oxide semiconductor.

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Material and electrical characterization of TMS-based silicidation of the Cu-dielectric barrier interface for electromigration improvement of 65nm interconnects

Cited by 7 publications

References 9 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Correlation between the Annealing Effect and the Electrical Characteristics of the Depletion Region in ZnO, SnO₂and ZTO Films

A Study on an Oxygen Vacancy and Conductivity of Oxide Thin Films Deposited by RF Magnetron Sputtering and Annealed in a Vacuum

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Material and electrical characterization of TMS-based silicidation of the Cu-dielectric barrier interface for electromigration improvement of 65nm interconnects

Cited by 7 publications

References 9 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Correlation between the Annealing Effect and the Electrical Characteristics of the Depletion Region in ZnO, SnO2and ZTO Films

A Study on an Oxygen Vacancy and Conductivity of Oxide Thin Films Deposited by RF Magnetron Sputtering and Annealed in a Vacuum

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Product

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Correlation between the Annealing Effect and the Electrical Characteristics of the Depletion Region in ZnO, SnO₂and ZTO Films