Massively multi-topology sizing of analog integrated circuits

Palmers,; McConnaghy,; Steyaert,; Gielen,

doi:10.1109/date.2009.5090756

Cited by 21 publications

(9 citation statements)

References 21 publications

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“…While reported approaches [8]- [10] not only fail to take care of the imposing dc performances while evaluating the topologies but also lack of global optimizer yields suboptimal design. Analytical expressions of performance metrics of a given topology as developed in [11]- [13] are used in [8][9] but with changing technology information, analytical expressions of even existing topologies change thus requiring the models to be regenerated for every topology. On the other hand, [14]- [16] ask for human intervention to develop performance expressions which make inclusion of new topologies hard.…”

Section: Introductionmentioning

confidence: 92%

A CAD methodology for automatic topology selection & sizing

Maji

Mandal

2011

2011 IEEE International SOC Conference

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Over the years, as system on chip is increasingly incorporating analog functionalities, there is a need of a tool, which can automate the analog topology selection and sizing flow. We develop one efficient methodology to automatically select the best topology given only the user specifications. The proposed topology selection is a multilevel screening process inherited from geometric programming (GP) by sequentially introducing sub-sets of requirements. This helps to prune out unfit topologies at early stage and hence not costing much computational effort. Use of GP ensures fast convergence with optimal solution. Apart from the speed advantage, compared to the existing literature, methodology has better representation of topology performance expressions. We propose to use two levels of performance expressions. First one is technology independent and the second one is technology specific. This bifurcation of performance expressions help in quick technology migration. Third contribution is automatic node expression generation which are required for dc performance evaluation. The proposed methodology is used for selecting optimal error amplifier topology for low dropout regulator (LDO).

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Section: Introductionmentioning

confidence: 92%

A CAD methodology for automatic topology selection & sizing

Maji

Mandal

2011

2011 IEEE International SOC Conference

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“…MOEA/D aroused many researchers interest as soon as it was proposed. Several improvements on MOEA/D have been made recently [18][19][20][21][22]. At the same time, MOEA/D has been successfully applied to a number of application areas [15,[23][24][25].…”

Section: Open Accessmentioning

confidence: 99%

Multiobjective Cloud Particle Optimization Algorithm Based on Decomposition

Wang

Jiang

et al. 2015

Algorithms

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Abstract:The multiobjective evolutionary algorithm based on decomposition (MOEA/D) has received attention from researchers in recent years. This paper presents a new multiobjective algorithm based on decomposition and the cloud model called multiobjective decomposition evolutionary algorithm based on Cloud Particle Differential Evolution (MOEA/D-CPDE). In the proposed method, the best solution found so far acts as a seed in each generation and evolves two individuals by cloud generator. A new individual is produced by updating the current individual with the position vector difference of these two individuals. The performance of the proposed algorithm is carried on 16 well-known multi-objective problems. The experimental results indicate that MOEA/D-CPDE is competitive.

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“…Instead, we validate a circuit by meaningfully introducing the performance constraints over several stages to quickly converge to the final circuit. Recent approaches like [16] [17] are more about blind search over a set of topologies and verifying their performances through spice simulation.…”

Section: Introductionmentioning

confidence: 99%

A geometric programming aided knowledge based approach for analog circuit synthesis and sizing

Maji

Mandal

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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A knowledge based approach empowered by geometric programming (GP) for analog circuit synthesis and sizing is presented. Analog circuit performance specification is mapped to various building blocks of a circuit topology. Then, the topology is modified according to the design rules in the library. Each modification is validated over two steps. In the first step, dc performance constraints are introduced. If qualified, ac performance constraints are introduced. Validation over two steps helps to gradually close in on input specifications removing any undesired correction made initially. It results in faster convergence.

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Massively multi-topology sizing of analog integrated circuits

Abstract: Abstract

Cited by 21 publications

References 21 publications

A CAD methodology for automatic topology selection & sizing

A CAD methodology for automatic topology selection & sizing

Multiobjective Cloud Particle Optimization Algorithm Based on Decomposition

A geometric programming aided knowledge based approach for analog circuit synthesis and sizing

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Massively multi-topology sizing of analog integrated circuits

Abstract: Abstract

Cited by 21 publications

References 21 publications

A CAD methodology for automatic topology selection &amp; sizing

A CAD methodology for automatic topology selection &amp; sizing

Multiobjective Cloud Particle Optimization Algorithm Based on Decomposition

A geometric programming aided knowledge based approach for analog circuit synthesis and sizing

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Product

Resources

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A CAD methodology for automatic topology selection & sizing

A CAD methodology for automatic topology selection & sizing