MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks

Sie, Syuan-Hao; Lee, Jye-Luen; Chen, Yiren; Yeh, Zuo-Wei; Li, Zhaofang; Lu, Chih‐Cheng; Hsieh, Chih-Cheng; Chang, Meng‐Fan; Tang, Kea-Tiong

doi:10.1109/tcad.2021.3082107

Cited by 13 publications

(5 citation statements)

References 33 publications

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“…Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org E datasets (such as CIFAR100, CIFAR10, and MNIST) [13,21,22]. However, some CNN-based industrial applications demand a reasonable classification accuracy on the ImageNet dataset [23].…”

Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

“…Inference of widely-used classification CNNs requires signed (or unsigned) format and signed format for data and weights, respectively [26]; signed format for both data and weights is usually needed for a finite impulse response (FIR) filter [5]; unsigned format for both data and weights is appropriate for Gaussian image filtering to gain higher accuracy compared with signed format with the same bit widths [27]. Some previous works have achieved bit-flexible convolution layers with signed/unsigned weights and unsigned inputs by assigning negative factors to the sign-bit CIM columns [13,21,22]. Saurabh Jain et al attempted to implement convolution layers with signed inputs/weights in SRAM-CIM using duplicated word lines, which cannot achieve flexible bit-width of weights.…”

Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

“…For hardware efficiency, two key metrics are considered: macro utilization [15] and normalized throughput [21]. The effectiveness of weight mapping strategies is evaluated based on the macro utilization, denoted as 𝑈 , which is calculated as (19).…”

Section: ) Evaluation Matricsmentioning

confidence: 99%

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A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

Bai,

Li,

Zhang

et al. 2024

Preprint

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Deploying convolution-based algorithms into SRAM computing-in-memory (CIM) systems faces various challenges, such as operator incompatibility and intrinsic non-ideal error. This paper proposes a compilation framework to address this issue. Efficient weight mapping strategies are introduced to improve the utilization of SRAM-CIM macro. The intrinsic non-ideal errors of SRAM-CIM macro are also taken into consideration, and two efficient error correction schemes are proposed, which include calibration of computation voltage linear error (CCVLE) and the mitigation of analog-to-digital quantization error (MAQE). In addition, bit-width flexibility and signed-unsigned reconfigurability are also supported to facilitate the deployment of various convolution-based algorithms. ResNet18, finite impulse response (FIR) filtering, and Gaussian image filtering are deployed into a multi-macro SRAM-CIM system. These algorithms serve as deployment representatives of convolutional neural network (CNN), digital signal processing (DSP), and digital image processing (DIP), respectively. The results show that the introduced weight mapping strategies improve the macro utilization by 63.29% and 21.10% for two types of frequently used convolution layers compared to the traditional strategy. Moreover, the proposed error correction schemes achieve similar algorithm accuracy to the floating-point results, and the deployment result of ResNet18 achieves 66.3%~70.1% top-1 classification accuracy evaluated on the ImageNet dataset with different throughput tradeoffs.

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Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

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A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

Bai,

Li,

Zhang

et al. 2024

Preprint

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“…In simple application scenarios, it has nearly the same accuracy as the traditional CNN algorithm [1,2] . Chih et al [75] proposed another solution that uses all-digital CIM to execute MAC operations and has high energy efficiency and throughput. In order to reduce computational costs, Sie et al [76] proposed a software and hardware co-design approach to design MARS.…”

Section: Parametermentioning

confidence: 99%

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Lin¹,

Tong²,

Zhang³

et al. 2022

J. Semicond.

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Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

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“…The emerging computing-in-memory (CIM) techniques address these shortcomings by performing the MAC operations directly upon reading the synaptic weights from the memory [5], [6], [7], [8], [9], [10], [11], [12]. The CIM circuit designs usually convert the ANN's digital inputs into analog signals to control the read wordlines (RWLs) of the memory cells whose responses are added in an analog way on the read bitlines (RBLs) to produce the analog MAC results.…”

mentioning

confidence: 99%

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

Chen,

Dai,

Hong

2024

IEEE Trans. VLSI Syst.

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This article demonstrates the first functional neuromorphic spiking neural network (SNN) that processes the time-to-first-spike (TTFS) encoded analog spiking signals with the second-order leaky integrate-and-fire (SOLIF) neuron model to achieve superior biological plausibility. An 8-kb SRAM macro is used to implement the synapses of the neurons to enable analog computing in memory (ACIM) operation and produce current-type dendrite signals of the neurons. A novel lowleakage 8T (LL8T) SRAM cell is proposed for implementing the SRAM macro to reduce the read leakage currents on the read bitlines (RBLs) when performing ACIM. Each neuron's soma is implemented with low-power analog circuits to realize the SOLIF model for processing the dendrite signals and generating the final analog output spikes. No data converters are required in our design by virtue of analog computing's nature. A test chip implementing the complete output layer of the proposed SNN was fabricated in 90-nm CMOS. The active area is 553.4 × 118.6 µm 2 . The measurement results show that our SNN implementation achieves an average inference latency of 196 ns and an inference accuracy of 81.4%. It consumes 242 µW with an energy efficiency of 4.74 pJ/inference/neuron.

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MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks

Cited by 13 publications

References 33 publications

A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

A review on SRAM-based computing in-memory: Circuits, functions, and applications

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

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