March

Chen, Jingsong; Liu, Jinwei; Chen, Gengjie; Zheng, Dan; Young, Evangeline F. Y.

doi:10.1145/3316781.3317860

Cited by 10 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[36] proposed an ILP-based track assignment algorithm to complete the channel routing. [37] proposed a maze routing method, which does not apply to signal wires assignment in VLSI.…”

Section: Related Workmentioning

confidence: 99%

SLDPSO-TA: Track Assignment Based on Social Learning Discrete Particle Swarm Optimization

Liu

Jing

Zhou

et al. 2023

Preprint

View full text Add to dashboard Cite

In the modern Very Large Scale Integration (VLSI) circuit design, the short-circuit problem is one of the key factors affecting routability. Due to the increased circuit size and net density, the short-circuit problem grows significantly in detailed routing. Furthermore, global routing ignores many problems in detailed routing, making for an increased mismatch between global routing and detailed routing. As a crucial intermediate phase between global routing and detailed routing, track assignment is an excellent phase to pre-process the short-circuit problem. However, existing track assignment algorithms face the problem of falling into local optimality. As one of the typical representatives of the swarm intelligence techniques, Particle Swarm Optimization (PSO) is a powerful tool to solve large-scale discrete problems. Therefore, we propose an effective Track Assignment Algorithm Based on Social Learning Discrete Particle Swarm Optimization (SLDPSO-TA). First, the proposed algorithm considers local nets to better guide detailed routing and an effective encoding method is designed to adapt the evolutionary algorithms better. Second, the social learning mode based on example pool mechanism is presented to improve the algorithm performance. Finally, a negotiation-based refining strategy is utilized to further reduce the overlap. Experimental results show that SLDPSO-TA can obtain the best overlap cost optimization among similar works, and reduce the congestion in key routing areas.

show abstract

“…[36] proposed an ILP-based track assignment algorithm to complete the channel routing. [37] proposed a maze routing method, which does not apply to signal wires assignment in VLSI.…”

Section: Related Workmentioning

confidence: 99%

SLDPSO-TA: Track Assignment Based on Social Learning Discrete Particle Swarm Optimization

Liu

Jing

Zhou

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

“…Kim et al [14] introduced a compact topologyaware bus routing approach capable of synthesizing the routing topology of the bus while minimizing design rule violations in designs with high bus density and track utilization. Chen et al [15] proposed a maze routing method to address non-uniform track resources using a concurrent and hierarchical scheme for buses, whereas Hsu et al [16] applied a directed acyclic graph (DAG)-based algorithm to connect buses and alleviate routing congestion through rip-up and rerouting. Additionally, Zhang et al [17] introduced the concept of topological Boolean satisfiability to verify the legality of a segment during the detailed routing stage and determine the existence of feasible bit ordering.…”

Section: Previous Workmentioning

confidence: 99%

A Novel Global Routing Algorithm for Printed Circuit Boards Based on Triangular Grid

Chen,

Zhou,

Liu

et al. 2023

Electronics

View full text Add to dashboard Cite

Global routing plays a crucial role in printed circuit board (PCB) design and affects the cost of the design significantly. Conventional methods based on rectangular grids have some limitations, whereas this paper introduces a new algorithm that employs a triangular grid model, which offers a more efficient solution to the problem. Firstly, we present a technique to sort all unconnected two-pin nets. Next, a triangular grid graph is constructed to represent the routing resources on the printed circuit board. Finally, we use the concept of maximum flow to identify the paths for global routing and apply detailed routing for the completion of wires. Results from experiments demonstrate that our algorithm is faster than two state-of-the-art routers and does not have any design rule violations for all industrial PCB instances.

show abstract