Mapping of MPEG-4 decoding on a flexible architecture platform

Tol, Erik B. van der; Jaspers, E.G.T.

doi:10.1117/12.451067

Cited by 94 publications

(53 citation statements)

References 21 publications

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“…       설명 mpeg4decode 9 3 12 MPEG4 디코더 [7] multimedia_soc 12 4 21 멀티미디어 SoC [3] mobile_mmp 12 5 20 모바일 멀티미디어 플레이어 [2] mobile_ap 14 5 21 모바일 어플리케이션 프로세서 [2] 표 1. 실험에 사용된 벤치마크 명세 Table 1.…”

Section: E-milp와 N-milp 방법 모두 C++로 구현되었으며unclassified

On-Chip Crossbar Network Topology Synthesis using Mixed Integer Linear Programming

Jun¹,

Chung²

2013

Journal of the Institute of Electronics and Information Enginee

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As the number of IPs and the communication volume among them have constantly increased, on-chip crossbar network is now the most widely-used on-chip communication backbone of contemporary SoCs. The on-chip crossbar network consists of multiple crossbars and the connections among the IPs and the crossbars. As the complexity of SoCs increases, it has also become more and more complex to determine the topology of the crossbar network. To tackle this problem, this paper proposes an on-chip crossbar network topology method for application-specific systems. The proposed method uses mixed integer linear programming to solve the topology synthesis problem, thus the global optimality is guaranteed. Unlike the previous MILP-based methods which represent the topology with adjacency matrixes of IPs and crossbar switches, the proposed method uses the communication edges among IPs as the basic element of the representation. The experimental results show that the proposed MILP formulation outperforms the previous one by improving the synthesis speed by 77.1 times on average, for 4 realistic benchmarks.

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Section: E-milp와 N-milp 방법 모두 C++로 구현되었으며unclassified

On-Chip Crossbar Network Topology Synthesis using Mixed Integer Linear Programming

Jun¹,

Chung²

2013

Journal of the Institute of Electronics and Information Enginee

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“…For the example of MPEG-4 decoder [9], the difference between the required capacity and the best and the worst mappings is about 203.04 per cent.…”

Section: Proposed Design Flowmentioning

confidence: 99%

Heuristics Core Mapping in On-Chip Networks for Parallel Stream-Based Applications

Dziurzański¹,

Maka²

2008

Computational Science – ICCS 2008

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Abstract.A novel approach for implementation of multimedia streaming applications into mesh Networks on Chips structure is proposed. We provide a new multi-path routing algorithm together with heuristic algorithms for core mapping so that minimize the total transfer in the hardware implementation. The proposed approach has been tested with two popular stream-based video decompression algorithms. The experimental results confirming the proposed approach are provided.

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“…Figure 9 shows the task graph and flow mapping of a Video Object Plane Decoder (VOPD) [39] in which each block corresponds to an IP and the numbers near the edges represent the bandwidth (in MBytes/sec) of the data transfer, for a 30 frames/sec MPEG-4 movie with 1920 × 1088 resolution [40]. There are 21 communication flows characterized by TSPEC.…”

Section: A Vopd Applicationmentioning

confidence: 99%

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Jafari

Jantsch

2016

IEEE Trans. VLSI Syst.

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Abstract-We propose an approach for computing the endto-end delay bound of individual variable bit-rate flows in a FIFO multiplexer with aggregate scheduling under Weighted Round Robin (WRR) policy. To this end, we use network calculus to derive per-flow end-to-end equivalent service curves employed for computing Least Upper Delay Bounds (LUDBs) of individual flows. Since real time applications are going to meet guaranteed services with lower delay bounds, we optimize weights in WRR policy to minimize LUDBs while satisfying performance constraints. We formulate two constrained delay optimization problems, namely, Minimize-Delay and Multiobjective optimization. Multi-objective optimization has both total delay bounds and their variance as minimization objectives. The proposed optimizations are solved using a genetic algorithm. A Video Object Plane Decoder (VOPD) case study exhibits 15.4% reduction of total worst-case delays and 40.3% reduction on the variance of delays when compared with round robin policy. The optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces. We conclude that an appropriate weight allocation can be a valuable instrument for delay optimization in on-chip network designs.

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Mapping of MPEG-4 decoding on a flexible architecture platform

Cited by 94 publications

References 21 publications

On-Chip Crossbar Network Topology Synthesis using Mixed Integer Linear Programming

On-Chip Crossbar Network Topology Synthesis using Mixed Integer Linear Programming

Heuristics Core Mapping in On-Chip Networks for Parallel Stream-Based Applications

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

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