Mapping of H.264 decoding on a multiprocessor architecture

Tol, Erik B. van der; Jaspers, E.G.T.; Gelderblom, Rob H.

doi:10.1117/12.476234

Cited by 103 publications

(67 citation statements)

References 10 publications

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“…Chong [9] added a pre-parsing stage in order to resolve control dependencies for MB-level parallelization. Van Der Tol [10] mapped video sequences data over multiple processors providing better performance over functional parallelization. He groups macroblocks in a way that minimal dependency between cores is required.…”

Section: Related Workmentioning

confidence: 99%

Design of the H264 application and Implementation on Heterogeneous Architectures

Adda¹,

Benyamina²

2017

IJCA

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Multimedia applications are present in most mobile hand-held devices.H.264 is an emerging video coding standard, which aims at compressing high-quality video contents at low-bit rates. While the new encoding and decoding processes are similar to many previous standards, the new standard includes a number of new features and thus requires much more computation than most existing standards do. The complexity of H.264 standard poses a large amount of challenges to implementing the encoder/decoder in real-time requiring large amount of processing resources. This paper presents the design and analysis of the H.264 decoder implemented on a heterogeneous architecture (multi-CPUs/multi-GPUs). A model-driven approach is adopted by using the standard MARTE profile of UML. Our approach is based on hybrid partitioning that combines both functional and data partitioning which is applied to find the most suitable processors (CPU or GPU) regarding the execution time. We claim that our approach allows giving a better performance, which is crucial when implemented in modern complex systems.

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Section: Related Workmentioning

confidence: 99%

Design of the H264 application and Implementation on Heterogeneous Architectures

Adda¹,

Benyamina²

2017

IJCA

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“…Using slices to separate the decoding frames can produce good parallel decoding efficiency. Van der Tol et al, [7] achieve parallel structure by taking each decoding procedure and separating it into various tasks and by assigning different tasks to different decoders.…”

Section: Internal Parallel Processingmentioning

confidence: 99%

Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system

Lai

Huang

Lai

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS) may be used for simpler calculations in order to decrease the system voltage or frequency and achieve lower power consumption. Combining these two mechanisms may lead to higher efficiency and lower power consumption. In this paper, we introduce a parallel decoding process with Digital Signal Processing (DSP) for power efficiency in a heterogeneous multicore embedded system. We describe a parallel low-power design on the system level. Under the condition of preserving the original decoding process, we manage the size of the system's multimedia buffer by considering the spontaneous streaming transfer and tuning the decoding process scheduling time by using the DVFS system in order to decrease the multimedia data dependency and achieve a multi-core embedded system with accurate and low-power detection mechanism.

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“…The H.264 benchmark is parallelized according to the method described in [6], contains 8160 tasks, with an average execution time of 8.1 . Each task depends on its left and top-right neighbors if they exists.…”

Section: Evaluation Of Nexusmentioning

confidence: 99%

Nexus: Hardware Support for Task-Based Programming

Meenderinck

Juurlink

2011

2011 14th Euromicro Conference on Digital System Design

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Abstract-To improve the programmability of multicores, several task-based programming models have recently been proposed. Inter-task dependencies have to be resolved by either the programmer or a software runtime system, increasing the programming complexity or the runtime overhead, respectively. In this paper we therefore propose the Nexus hardware task management support system. Based on the inputs and outputs of tasks, it dynamically detects dependencies between tasks and schedules ready tasks for execution. In addition, it provides fast and scalable synchronization. Experiments show that compared to a software runtime system, Nexus improves the task throughput by a factor of 54 times. As a consequence much finer-grained tasks and/or many more cores can be efficiently employed. For example, for H.264 decoding, which has an average task size of 8.1 , Nexus scales up to more than 12 cores, while when using the software approach, the scalability saturates at below three cores.

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Mapping of H.264 decoding on a multiprocessor architecture

Cited by 103 publications

References 10 publications

Design of the H264 application and Implementation on Heterogeneous Architectures

Design of the H264 application and Implementation on Heterogeneous Architectures

Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system

Nexus: Hardware Support for Task-Based Programming

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