Mapping application‐specific topology to mesh topology with reconfigurable switches

Abstract

When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors' method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.

Discrete Firefly Algorithm for Optimizing Topology Generation and Core Mapping of Network-on-Chip

“…In [7], authors have presented a discussion on the trends in system-on-chip designs and the evolution of Network on Chip (NoC). An irregular topology generation using genetic algorithm has been proposed in [8] as a two-step method combining the benefits of both regular and irregular topologies. This generated topology is area and energy optimized.…”

“…Now, each 'nm' position is indicated by a variable having 2 indices g k,l . In this, 'k' and 'l' represent the router index and port number respectively [8]. The position of a particular node in the string can be represented as gP k,l , and can be calculated as in Eq.…”

“…For example, the two topology strings of MP3 Encoder application are considered. Difference {(2,0), (3,5), (4,7), (6,3), (8,11), (10,8), (16,9), (20,4)…”

“…In the list of random numbers generated the positions whose values are lower than β(r) are exchanged with the P best . Now the position after exchange is: {(3,5), (4,7), (6,3), (8,11), (16,9)}. So, after the exchange mechanism process, the topology is changed as {−1 7 5 7 −2 3 −1 11 −3 0 −2 -4 2 −4 1 9 10 6 −3 8}.…”

“…But this placement of nodes is not always possible practically every time. To shorten the hop distances between nodes of the mesh topology, the concept of reconfigurable switches is applied [8]. These switches offer alternative fast routes between remote routers.…”