Many-Core Token-Based Adaptive Power Gating

Kahng, Andrew B.; Kang, Seokhyeong; Rosing, Tajana; Strong, Richard

doi:10.1109/tcad.2013.2257923

Cited by 22 publications

(15 citation statements)

References 19 publications

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“…This partitioning and refreshing saves energy at the cost of a slightly increased data error in the non-critical data.Flikker thus finds an interesting trade-off between energy consumption and hardware correctness. Token-Based Adaptive Power Gating (TAP) [13], a technique to power gating the cores during memory accesses, TAP works by observing and predicting the system memory request power gate the core without performance or energy loss. A mixed approach for the same goal is presented in [2] the literature describe a simple power down policy for exploiting low power modes of DRAMs, with adaptive history-based memory schedulers and throttling approach that arbitrarily reduces DRAM activity by delaying the issuance of memory commands.…”

Section: Literature Reviewmentioning

confidence: 99%

An Efficient DRAM with Reduced Energy Consumption in Video Driver

Khan¹,

Beohar²,

Gurjar³

2014

IJCA

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Power reduction in electronic and computing system is one of the basic requirements and is increasingly demanded for the battery operated mobile systems. Although the power is required for every part of the system but the devices accessed most frequently (processor, DRAM) are takes special attention, because the improvement in power dissipation in these devices can dramatically reduce the overall power requirement. Since the many approaches have been already proposed for the power reduction in processor this paper focuses on the power reduction in DRAM. The DRAM may be considered as most power consuming device after processor, even when it is idle. Although the DRAMs inherently supports different power saving modes, like selfrefresh and power-down, but these techniques are not as efficient and also causes the unwanted delay which in noncomprisable for the many multimedia applications. Hence in this paper, we propose and evaluate an efficient DRAM rank grouping and power gating technique for power-saving that optimizes the power saving with marginal performance degradation. The proposed approach is developed and tested on several multimedia operations and the experimental results show that it reduces the total DRAM energy consumption between 56% and 183%(approx)at a negligible performance penalty between 3% and 5%(approx).

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Section: Literature Reviewmentioning

confidence: 99%

An Efficient DRAM with Reduced Energy Consumption in Video Driver

Khan¹,

Beohar²,

Gurjar³

2014

IJCA

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“…A Token-based Adaptive Power gating (TAP) approach to actively power gate the core during memory access in many core systems is discussed in [15]. TAP tracks the memory request and its estimated arrival time for power gating the core.…”

Section: Related Workmentioning

confidence: 99%

“…In designing the on-chip dual-band transceiver, design considerations are taken into account at architecture level with a design adopted from ( [15], [16], [17]). Non-coherent on-off keying (OOK) modulation scheme is used here.…”

Section: Dual-band Wireless Transceiver Circuit With Antennamentioning

confidence: 99%

An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip

Mondal

Harsha

Deb

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Networks-on-Chip (NoC) have emerged as communication backbones for enabling high degree of integration in future many-core chips. Despite their advantages, the communication is multi-hop and causes high latency and power dissipation, especially in larger systems. Wireless Network-on-Chip (WNoC) significantly improves the latency over traditional wired NoCs for multi-core systems. But on-chip wireless interfaces (WIs) have their own power and area overhead. In this paper we design and implement a Dynamic Voltage Frequency Scaling (DVFS) technique and extend it to provide power gating to the WIs. This approach effectively reduces the energy consumption in multi core systems. A centralized controller with dual-band wireless transceiver implements per-core DVFS. The scheme ensures balanced workload and energy consumption of the chip and efficient power gating for the WIs. It helps to alleviate the power consumption up to 33.085 % for on-chip communications infrastructure with little overheads.Keywords-wireless network-on-chip; dual-band transceiver and antenna; dynamic voltage and frequency; low power

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“…ARGO and the aging-oblivious allocator meet the target frequency of 800MHz at the worst-case corner. Regarding the wake-up latency from the sleep state, recent efforts [32], [33], [43] have shown the latency is less than ten cycles for a power-gated cell. Due to availability of other ready wavefronts in the queue, these ten cycles are effectively hidden.…”

Section: Argo Overheadmentioning

confidence: 99%

ARGO: Aging-aware GPGPU register file allocation

Namaki-Shoushtari¹,

Rahimi²,

Dutt³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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State-of-the-art general-purpose graphic processing units (GPGPUs) implemented in nanoscale CMOS technologies offer very high computational throughput for highly-parallel applications using hundreds of integrated on-chip resources. These resources are stressed during application execution, subjecting them to degradation mechanisms such as negative bias temperature instability (NBTI) that adversely affect their reliability. To support highly parallel execution, GPGPUs contain large register files (RFs) that are among the most highly stressed GPGPU components; however we observe heavy underutilization of RFs (on average only 46%) for typical general-purpose kernels. We present ARGO, an Aging-awaRe GPGPU RF allOcator that opportunistically exploits this RF underutilization by distributing the stress throughout RF. ARGO achieves proper leveling of RF banks through deliberated power-gating of stressful banks. We demonstrate our technique on the AMD Evergreen GPGPU architecture and show that ARGO improves the NBTI-induced threshold voltage degradation by up to 43% (on average 27%), that yields improving RFs static noise margin up to 46% (on average 30%). Furthermore, we estimate a simultaneous reduction in leakage power of 54% by providing sleep states for unused banks.

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Many-Core Token-Based Adaptive Power Gating

Cited by 22 publications

References 19 publications

An Efficient DRAM with Reduced Energy Consumption in Video Driver

An Efficient DRAM with Reduced Energy Consumption in Video Driver

An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip

ARGO: Aging-aware GPGPU register file allocation

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