Manufacturing Testing and Security Countermeasures

Natale, Giorgio Di; Flottes, Marie-Lise; Rouzeyre, Bruno; Pugliesi-Conti, Paul-Henri

doi:10.1007/978-3-319-44318-8_7

Cited by 3 publications

(3 citation statements)

References 29 publications

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“…This can be done by physically connecting the output of the scan controller to a pull-up element or a controllable source. The former is based on the Saw Bow method [19], where the connecting wire crosses the sawing line of the wafer. The latter is depicted in Fig.…”

Section: A Scan Controllermentioning

confidence: 99%

A Secure Scan Controller for Protecting Logic Locking

Nguyen

Valea

Flottes

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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The globalized supply chain in the Integrated Circuit (IC) industry raises several security concerns such as overproduction, IP piracy and Hardware Trojan insertion. Logic locking has emerged as a potential countermeasure to address these issues. However, its efficiency is challenged by various attacks, especially oracle-guided attacks based on Boolean Satisfiability (SAT) solvers. These attacks rely on the possibility for an attacker to control and observe in the field the internal state of a functional IC, which acts as an oracle. This ability to control/observe the IC states is offered by scan chains, typically used for IC production testing. In this paper, we propose a method, complementary to logic locking, to prevent such attacks. This method introduces a scan chain controller with a key-based authentication mechanism, in order to prevent unauthorized access to the scan chains once the IC is deployed in the field. The solution can be coupled with any logic locking technique at the cost of negligible area overhead. Furthermore, it is secure against state-of-the-art attacks and supports full testing.

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Section: A Scan Controllermentioning

confidence: 99%

A Secure Scan Controller for Protecting Logic Locking

Nguyen

Valea

Flottes

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…The strong pull-up resistance sets a logic value on the line when the sawing line is intact. When the dies are sawed, the weak pull-down resistance sets the opposite value on the line [11].…”

Section: ) Wafer Testingmentioning

confidence: 99%

Encryption-Based Secure JTAG

Valea

Silva

Flottes

et al. 2019

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Standard test infrastructures, such as IEEE Std. 1149.1 (JTAG), IEEE Std. 1500 and IEEE Std. 1687 (IJTAG), are widely used in nowadays Integrated Circuits (ICs). However, they pose an important security challenge to the designers because of the high controllability and observability they offer through the Test Access Port (TAP). For instance, malicious users can exploit test infrastructures in order to access the internal scan chains of crypto-cores and perform scan attacks. Moreover, these infrastructures connect all the devices of the system to the same network. For this reason, the data sent to a target device are potentially visible to all the others. Consequently, this poses a threat to the confidentiality of data content. The encryption of test data is a countermeasure that has been conceived in order to overcome these threats. In this paper, we propose a new secure version of the JTAG infrastructure, relying on stream-based encryption.

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“…In comparison with previous survey papers [52]- [54], this paper has two main contributions. Firstly, from the perspective of scan chain based attacks, this paper introduces the two phases, scan data obtaining and scan data analysis respectively to detail the attack process.…”

Section: Introductionmentioning

confidence: 99%

Scan Chain Based Attacks and Countermeasures: A Survey

et al. 2019

IEEE Access

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Scan chains increase the testability but decrease security. Attackers may use scan chains to launch attacks to obtain sensitive information, which poses serious security threats. The scan chain-based attacks contain two steps: 1) scan data obtaining, including mode switching obtaining method and test mode only obtaining method, and 2) scan data analysis, including data mapping analysis method and signature analysis method. To prevent these attacks, various secure scan designs have been proposed. These designs are summarized into two categories: scan chain modification and scan input/output restriction. This paper gives a survey of the scan chain-based attacks and countermeasures. The secure scan designs are summarized and compared from the aspects of security, testability, test time, and hardware overhead.INDEX TERMS Scan chain based attacks, test mode, mode switch, signature, secure scan chain, secret key, physical unclonable function.

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Manufacturing Testing and Security Countermeasures

Cited by 3 publications

References 29 publications

A Secure Scan Controller for Protecting Logic Locking

A Secure Scan Controller for Protecting Logic Locking

Encryption-Based Secure JTAG

Scan Chain Based Attacks and Countermeasures: A Survey

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