Manufacturing and Characterization of III-V on Silicon Multijunction Solar Cells

Veinberg‐Vidal, Elias; Dupré, C.; García‐Linares, Pablo; Jany, Christophe; Thibon, Romain; Card, T.; Salvetat, T.; Scheiblin, P.; Brughera, Céline; Fournel, Frank; Désières, Y.; Veschetti, Y.; Sanzone, V.; Mur, P.; Décobert, J.; Datas, Alejandro

doi:10.1016/j.egypro.2016.07.066

Cited by 12 publications

(5 citation statements)

References 7 publications

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“…This difference was clearly attributed to the replacement of the Pd NPs with the Cu NRs because other components were identical. It has been reported that this so-called S-shaped J–V curve arises when the metal/semiconductor interface has a potential barrier, which acts as a reverse diode. − Three plausible reasons were considered for the potential barrier formation with the Cu NR array: (1) the inherent difficulty in forming ohmic-like (low resistance) contacts among the GaAs, Cu NRs, and Si used in this study owing to their original material properties, such as doping levels and work functions, (2) insufficient physical contacts between Cu NRs and upper GaAs because the surface morphology of the Cu NRs looked irregular (bumpy) in the SEM and AFM images, or (3) poor electrical contacts between Cu NRs and the bottom Si because the surface of the employed Si cell was capped with a native-oxide layer (although this did not matter in the case of the Pd NP array). It was found, however, that the preparation of Cu NR arrays on native-oxide-removed c-Si surfaces was difficult to achieve using Method A because undesired micron-scale Cu precipitates grew at pinholes in the spin-coated PS- b -P2VP template during the Cu 2+ ion loading through galvanic displacement , (Figure S1).…”

Section: Resultsmentioning

confidence: 99%

Cu Nanoparticle Array-Mediated III–V/Si Integration: Application in Series-Connected Tandem Solar Cells

Mizuno

Makita

Mochizuki

et al. 2020

ACS Appl. Energy Mater.

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The integration of III−V materials with crystalline Si (c-Si) is a promising pathway to design high-performance optoelectronic devices, including solar cells. We have previously reported high-efficiency III−V/Si tandem cells using our unique semiconductor bonding technique, termed smart stack. In the conventional smart stack cells, Pd nanoparticle (NP) arrays have been commonly employed as bonding mediators between III−V and c-Si; however, from an economical point of view, the use of other low-cost metals would be preferable. Therefore, this study focused on the possibility of Cu. A polystyrene-block-poly-2-vinylpyridine (PS-b-P2VP)-based block copolymer was utilized to prepare Cu NP arrays. Desired Cu NP arrays were achieved by starting with self-assembled PS-b-P2VP micelles preloaded with Cu 2+ ions. Satisfying bonding properties (low-resistance interfaces) were confirmed when GaAs subcells were stacked on the Cu NP arrays formed on native-oxide-removed c-Si subcells. Conversion efficiencies of up to 25.9% have been demonstrated with triple-junction structures consisting of InGaP/GaAs top and c-Si bottom subcells. The long-term reliability of Cu NP array-mediated smart stack cells was also verified by the thermal cycle and damp heat tests. Hence, we have successfully confirmed that not only Pd but also Cu is available to realize high-efficiency smart stack cells.

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Section: Resultsmentioning

confidence: 99%

Cu Nanoparticle Array-Mediated III–V/Si Integration: Application in Series-Connected Tandem Solar Cells

Mizuno

Makita

Mochizuki

et al. 2020

ACS Appl. Energy Mater.

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“…1) are etched away respectively by H2O2+NH4OH and HCl/H3PO4 solutions, leaving the fewmicrometers-thick III-V active layers on the Si bottom cell. 5) Finally, front metal contacts designed for low concentration (~20 suns, ~5% shading factor without bus bars [9]) and full sheet back metal contacts are deposited by evaporation. Mesa etching (trenches down to 2 μm inside Si) is performed to partially isolate individual cells of 1 or 2 cm² and a 65 nm Si3N4 Anti-Reflection Coating (ARC) is deposited by PECVD.…”

Section: A Sample Preparationmentioning

confidence: 99%

Wafer-Bonded AlGaAs///Si Dual-Junction Solar Cells

Veinberg‐Vidal

Vauche

Weick

et al. 2017

2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)

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Monolithic two-terminal III-V on Si dual-junction (2J) solar cells were fabricated by means of Surface-Activated direct wafer Bonding (SAB). Al0.2Ga0.8As single-junction cells are grown on GaAs substrate by Metal-Organic Vapor Phase Epitaxy (MOVPE) and bonded at room temperature to independently fabricated Si solar cells. The n + -GaAs//n + -Si bonding interface is characterized by Transmission Electron Microscopy (TEM) revealing a 2-3 nm thick amorphous interlayer. The performance of the 1 cm² tandem cells, designed for low concentration applications, was studied by External Quantum Efficiency (EQE)and J-V measurements showing a power conversion efficiency of 17% under one-sun AM1.5G spectrum. To our knowledge, this is the highest efficiency ever reported for a wafer-bonded 2J III-V on Si solar cell. Limitations to performance have been identified and therefore higher efficiencies are expected.

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“…Also, direct wafer bonding without adhesive or solder, such as hydrophilic, hydrophobic, and plasmaassisted bonding, can be applied to fabricate the heterointerfaces. [6][7][8][9] The method requires, however, high-temperature annealing to obtain sufficient bonding strength 10) that can induce the intermixing of dopants and mechanical defects across the heterointerfaces. Alternatively, surface-activated bonding (SAB) at room temperature, 11) in which surfaces of substrates are activated before bonding by creating dangling bonds via the removal of contaminants under an energetic particle bombardment in high vacuum, is applied to form tough Si=III-V heterointerfaces without macro defects.…”

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confidence: 99%

Intrinsic microstructure of Si/GaAs heterointerfaces fabricated by surface-activated bonding at room temperature

Ohno¹,

Yoshida²,

Takeda³

et al. 2017

Jpn. J. Appl. Phys.

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The intrinsic microstructure of Si/GaAs heterointerfaces fabricated by surface-activated bonding at room temperature is examined by plane-view transmission electron microscopy (TEM) and cross-sectional scanning TEM using damage-free TEM specimens prepared only by mechanochemical etching. The bonded heterointerfaces include an As-deficient crystalline GaAs layer with a thickness of less than 1 nm and an amorphous Si layer with a thickness of approximately 3 nm, introduced by the irradiation of an Ar atom beam for surface activation before bonding. It is speculated that the interface resistance mainly originates from the As-deficient defects in the former layer.

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Manufacturing and Characterization of III-V on Silicon Multijunction Solar Cells

Cited by 12 publications

References 7 publications

Cu Nanoparticle Array-Mediated III–V/Si Integration: Application in Series-Connected Tandem Solar Cells

Cu Nanoparticle Array-Mediated III–V/Si Integration: Application in Series-Connected Tandem Solar Cells

Wafer-Bonded AlGaAs///Si Dual-Junction Solar Cells

Intrinsic microstructure of Si/GaAs heterointerfaces fabricated by surface-activated bonding at room temperature

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