Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Beeck, Maaike Op de; Versluijs, Janko; Wiaux, Vincent; Vandeweyer, T.; Ciofi, Ivan; Struyf, Herbert; Hendrickx, Dirk; Olmen, J. Van

doi:10.1117/12.713393

Cited by 13 publications

(7 citation statements)

References 2 publications

(2 reference statements)

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“…One way to compensate for this difference consists of using different OPC features for the different patterns [16]. In ST-DPL, this method is no longer possible since the same mask is used for the first and second exposures.…”

Section: B St-dpl Challenges and Downsidesmentioning

confidence: 99%

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Ghaida

Torres

Gupta

2011

IEEE Trans. Semicond. Manufact.

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Abstract-1 We propose shift-trim double patterning lithography (ST-DPL), a cost-effective double patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double-patterning (ST-DPL as well as standard DPL). 2× pitch relaxation being associated with a considerable area overhead, 1.8× pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<0.3% cell-area overhead) and no more than 4.7% cellarea overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double-patterning: (1) cuts mask-cost to nearly half, (2) reduces overlay errors between the two patterns, (3) alleviates the bimodal line-width distribution problem in double patterning, and (4) slightly enhances the throughput of critical-layer scanners.

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Section: B St-dpl Challenges and Downsidesmentioning

confidence: 99%

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Ghaida

Torres

Gupta

2011

IEEE Trans. Semicond. Manufact.

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“…Therefore, the smallest half-pitch of contact holes is limited to ~50nm in the manufacturing process. 1 In order to overcome the theoretical resolution limit, various double patterning schemes were proposed in recent years including self-aligned double patterning (SADP), 2-5 litho-etch-litho-etch (LELE), [5][6][7] and litho-litho-etch (LLE). 8-15 While tool vendors have focused their efforts on SADP and LELE, most resist vendors have supported LLE that requires less process steps and lower cost of ownership than SADP and LELE.…”

Section: Introductionmentioning

confidence: 99%

Advanced patterning solutions based on the "shrink process assisted by double exposure" (SPADE)

Bae¹,

Liu²,

Cardolaccia³

et al. 2010

SPIE Proceedings

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By combining chemical and thermal curing techniques, we developed a simple "hybrid" curing system which offers precise CD control of the first patterns after double patterning. This hybrid curing system involves thermal curing followed by a liquid rinse process using a double patterning primer (DPP). DPP is an aqueous solution formulated with surface curing agent (SCA) components and enhances "positive" interaction between L1 and L2 patterns. Taking advantage of the CD growth with DPP treatment, we further developed three advanced patterning schemes: 1. "Shrink Process Assisted by Double Exposure" (SPADE TM I Process), 2. "Space Patterning Assisted by Double Exposure" (SPADE II), and 3. "Sidewall Patterning Assisted by Double Exposure" (SPADE III). Using SPADE I, contact hole CD was reduced by 10~30nm and excellent through pitch performance was achieved. Using SPADE II, the first example of self-aligned double patterning of contact holes has been demonstrated. After SPADE II, the contact hole pitch was reduced by 30%. A novel method was developed to form sidewalls on the existing patterns using SPADE III. The 2D sidewall patterning with contact holes was demonstrated and ~40nm sidewalls were formed using SPADE III. This can also be applied to form sidewall patterns on line and space patterns to self-aligned double patterning of lines. In this paper, our recent progress with SPADE technology is described and its potential use in the advanced patterning schemes is discussed.Keywords: double patterning primer, self-aligned double patterning, SPADE, shrink process assisted by double exposure (SPADE I), space patterning assisted by double exposure (SPADE II), sidewall patterning assisted by double exposure (SPADE III),

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“…It requires pattern being decomposed into two separate pattern sets, using a litho-etch-litho-etch approach on hard mask [1]. In each of the single exposure step, we can relax the dense pattern pitches by decomposing them into two half-dense ones.…”

Section: Introductionmentioning

confidence: 99%

A new OPC method for double patterning technology

Pan

Chen

2008

Optical Microlithography XXI

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As the VLSI technology scales into deep submicron nodes, Double Patterning Technology (DPT) has shown its necessity for the under 45nm processes. However, the litho-related and process-related issues, such as the overlay control for CD uniformity, decomposition, feature stitching technology and some other problems make up the main challenges for the implementation of DPT. Due to Optical Proximity Correction (OPC), the complexity and data volume of DPT increase dramatically, which severely increase the application cost and create manufacturability problems.In this paper, we mainly talk about the interactions between DPT and OPC and propose a new Model-Based OPC methods for the decomposition in DPT procedures. To address the printing problems with cutting sites for feature split, we introduce an overlap correction method on the stitching locations. For any re-cut and/or redesigned pattern after verification, we categorize DP decompositions and introduce a new Adaptable OPC (Ad-OPC) algorithm by reusing post OPC layout to speed up the correction and improve its convergence according to environment surrounding. The method can be easily incorporated into existing MB-OPC framework. To test this method, total Edge Placement Error (EPE) and runtime are calculated in our experiments. Results show that over 90% runtime can be saved compared with conventional OPC procedure. It increases the robustness and friendliness of pattern correction as well as stitches features back satisfactorily.

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Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Cited by 13 publications

References 2 publications

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Advanced patterning solutions based on the "shrink process assisted by double exposure" (SPADE)

A new OPC method for double patterning technology

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