Managing static leakage energy in microprocessor functional units

Abstract

Abstract

Modeling and Characterizing Power Variability in Multicore Architectures

“…We choose floating-point resources because they are not used by integer applications and hence are a likely candidate for leakage management techniques such as standby power modes or powergating [16,20]. The insight is that if there is significant vari- ation in power across cores for a given functional unit, we may benefit from selecting specific applications to run on appropriate cores.…”

Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization

“…Techniques have been proposed to reduce static power consumption of various microprocessor components which include Level 1 12 and Level 2 Caches [16,17,18,9] and Functional/Execution Units [10,6,19]. Additional hardware support is needed to reduce static power consumption of various microarchitectural components, which is discussed below.…”

“…The components can be put into a low leakage state either by (1) [20,26] and the third technique is the Input Vector Control [25,28].…”

Temperature aware task sequencing and voltage scaling

“…This is because power consumption depends on the circuit activity factor that can vary significantly across tasks [16]. Moreover, modern low-power processors engage aggressive clock gating and static power saving techniques [6], [9], [8] where the idle functional units are either clock gated or completely switched off. The power consumption in such a scenario depends heavily on the usage pattern of the functional units, which again varies significantly across tasks.…”