Managing standby and active mode leakage power in deep sub-micron design

Abstract

Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

“…Scaling V dd slows a circuit down since the gate overdrive V gs − V th is reduced. To deal with this, [22] suggests using dynamic voltage scaling for systems to allow the lowest V dd necessary to meet performance requirements. The subthreshold slope S can be made smaller by using a thinner oxide (insulator) layer to reduce T ox or a lower substrate doping concentration (resulting in larger W dm ).…”

Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications

“…A deep depletion condition is created since the holes are rapidly swept out. This leakage mechanism is exacerbated by high source or drain to body voltages as well as high drain to gate voltages [19]. GIDL effect can be minimized by carefully controlling the doping profile in the drain of an MOS transistor.…”

Power minimisation techniques at the RT-level and below

“…In addition, the different channel lengths track each other over process variation. This technique can be applied in a greedy manner to an existing design to limit the leakage currents [55]. A potential penalty is that the dynamic power dissipation of the up-sized gate is increased proportional to the effective channel length increase.…”