Managing multi-configuration hardware via dynamic working set analysis

Dhodapkar, Ashutosh S.; Smith, James E.

doi:10.1109/isca.2002.1003581

Cited by 168 publications

(232 citation statements)

References 22 publications

(32 reference statements)

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“…Prior work can be categorized into methods that define and use metrics to dynamically identify phases for adaptive optimization [5,6,8,13,26], and into techniques that identify appropriate simulation points for the desired workloads [10,16,17,24,25].…”

Section: Related Workmentioning

confidence: 99%

“…Several microarchitectural designs [3,5,6,8,11,13,15,18,21,31] have been proposed that allow the rapid low-cost adaptation of processor components to match hardware complexity and speed with an application's requirements. There have also been several approaches to dynamically adapt the software, such as application code, data placement, or runtime resource allocation.…”

Section: Introductionmentioning

confidence: 99%

“…Al-ternatively, profiling has been used to predict performance for future executions of the program [15,18]. There have also been studies that attempt to characterize and classify program behavior into phases, where phases are defined as regions of a program with relatively stable behavior [8,26]. The goal in these papers is the dynamic identification of phases in order to tune resources to meet the application needs.…”

Section: Introductionmentioning

confidence: 99%

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Characterizing and predicting program behavior and its variability

Duesterwald

Caşcaval

Dwarkadas

Oceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)

138

111

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Characterizing and predicting program behavior and its variability

Duesterwald

Caşcaval

Dwarkadas

Oceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)

138

111

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show abstract

“…First, existing techniques do not adequately capture the distinct phases of memory resource usage during an application's lifetime; working sets typically model the resource requirement for a fixed phase in the application while MRCs unify multiple phases into one, losing important distinctions between their individual resource consumption characteristics. Second, existing models focus on a specific level of memory; working sets are used for main memory [6] and MRCs for caches [9]. With the increasingly diverse levels of memory resources (L1, L2, L3, main memory, flash, and disks), a unified view of all memory resources is critically important for memory provisioning.…”

Section: Gaps In Existing Models and Characterizationmentioning

confidence: 99%

“…Balasubramonian et al [34] use the dynamic count of conditional branches to measure working set changes. Dhodapkar et al compute a working set signature and detect a phase change when the signature changes significantly [9].…”

Section: Mechanisms To Build Memory Usage Modelsmentioning

confidence: 99%

Generalized ERSS tree model: Revisiting working sets

Koller

Verma

Rangaswami

2010

Performance Evaluation

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Accurately characterizing the resource usage of an application at various levels in the memory hierarchy has been a long-standing research problem. Existing characterization studies are either motivated by specific allocation problems (e.g., memory page allocation) or they characterize a specific memory resource (e.g., L2 cache). The studies thus far have also implicitly assumed that there is no contention for the resource under consideration. The inevitable future of virtualization driven consolidation necessitates the sharing of physical resources at all levels of the memory hierarchy by multiple virtual machines (VMs). Given the lack of resource isolation mechanisms at several levels of the memory hierarchy within current commodity systems, provisioning resources for a virtualized application not only requires a precise characterization of its resource usage but must also account for the impact of resource contention due to other co-located applications during its lifetime. In this paper, we present a unifying Generalized ERSS Tree Model that characterizes the resource usage at all levels of the memory hierarchy during the entire lifetime of an application. Our model characterizes capacity requirements, the rate of use, and the impact of resource contention, at each level of memory. We present a methodology to build the model and demonstrate how it can be used for the accurate provisioning of the memory hierarchy in a consolidated environment. Empirical results suggest that the Generalized ERSS Tree Model is effective at characterizing applications with a wide variety of resource usage behaviors.

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Cooperative Caching for Chip Multiprocessors

Chang¹,

Herrero²,

Canal³

et al. 2011

Cooperative Networking

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Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these challenge, we propose CMP cooperative caching (CC), a unified framework to efficiently organize and manage on-chip cache resources. By forming a globally managed, shared cache using cooperative private caches. CC can effectively support two important caching applications: (1) reduction of average memory access latency and (2) isolation of destructive inter-thread interference.CC reduces the average memory access latency by balancing between cache latency and capacity optimizations. Based private caches, CC naturally exploits their access latency benefits. To improve the effective cache capacity, CC forms a "shared" cache using replication control and LRU-based global replacement policies. Via cooperation throttling, CC provides a spectrum of caching behaviors between the two extremes of private and shared caches, thus enabling dynamic adaptation to suit workload requirements. We show that CC can achieve a robust performance advantage over private and shared cache schemes across different processor, cache and memory configurations, and a wide selection of multithreaded and multiprogrammed workloads.To isolate inter-thread caching interference, we add a time-sharing aspect on top of spatial cache partitioning. Our approach uses Multiple Time-sharing Partitions (MTP) to simultaneously improve throughput and fairness while maintaining QoS over the longer term. Each MTP partition unfairly improves at least one thread's throughput, and partitions favoring different threads are scheduled in a cooperative, timesharing manner to either maintain fairness and QoS, or implement priority. We also integrate MTP with CC's LRU-based capacity sharing policy to combine their benefits. The integrated scheme-Cooperative Caching Partitioning (CCP)-divides the total execution epochs into those controlled by either MTP or the ii baseline CC policy, respectively, according to the fraction of threads that can benefit from each of them. Our simulation results show that for a wide range of multiprogrammed workloads, CCP can improve throughput, fairness and QoS for workloads suffering from destructive interference, while achieving the performance benefit of the baseline CC policy for other workloads.iii

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Managing multi-configuration hardware via dynamic working set analysis

Cited by 168 publications

References 22 publications

Characterizing and predicting program behavior and its variability

Characterizing and predicting program behavior and its variability

Generalized ERSS tree model: Revisiting working sets

Cooperative Caching for Chip Multiprocessors

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