Management of parasitic bipolars in modular high power LDMOS technology

Agam, Moshe; Pjencak, Jaroslav; Prejda, Dusan; Suwhanov, Agajan; Yao, T.; Seliga, Ladislav

doi:10.1109/essderc.2016.7599646

Cited by 9 publications

(1 citation statement)

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“…To a great extent it is dependent on device dimensions and physical parameters [5]. Various approaches are discussed in [5], [6], [7] to reduces the influence of parasitic BJT. Generally additional deep p+ region is included to minimize this effect.…”

Section: Introductionmentioning

confidence: 99%

Enhancement in the Design of VDMOS for Elimination of Parasitic BJT

Prasad,

Sahu,

Parmar

2023

Preprint

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This work provides solution to wipe out the effect of inherent parasitic bipolar junction transistor(BJT) present in the conventional power MOSFET. In this design, source and drain doping is eliminated from the design process using charge plasma technique leading to the removal of parasitic BJT from the device. A vertical metal oxide-semiconductor field effect transistor(VMOS) is proposed employing this technique. It is simulated and compared with the conventional vertical double diffused metal-oxide-semiconductor field effect transistor(VDMOS). In this work, proposed VMOS is also tested with various materials that can be used for plasma formation. When compared to the conventional VDMOS, the proposed VMOS exhibits 54.21% increment in breakdown voltage, 55.03% reduction in ON-resistance and approximately two times of the drain current density.

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Section: Introductionmentioning

confidence: 99%

Enhancement in the Design of VDMOS for Elimination of Parasitic BJT

Prasad,

Sahu,

Parmar

2023

Preprint

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Design of SEE-Tolerant analog switch chip with a novel diode structure ^*

Huang,

Liu,

2024

Nanotechnology

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This paper proposes a novel circuit-level design in order to enhance the radiation tolerance of an analog switch integrated circuit (IC). After analyzing the mechanisms of single-particle sensitivity in a high-voltage analog switch chip fabricated using a commercial 1-μm complementary metal–oxide–semiconductor (CMOS) process, a diode unit was employed to reduce the VGS (voltage between the gate and the base) of the parasitic triode within the metal–oxide–semiconductor field-effect transistor (MOSFET) of the switch. This reduction lowered the probability of activating the parasitic triode in response to single-event effect (SEE). Subsequently, single-particle irradiation experiments proceeded with the high-voltage analog switch chip, both with and without the diode unit. In the unreinforced device, the current of the power supply reached 100 mA within 11 s of single-particle irradiation at 75.8 MeV•cm2/mg. In contrast, in the reinforced device, the current of the power supply remained relatively stable under irradiation at both 37.2 and 75.8 MeV•cm2/mg. These findings indicate that the reinforced analog switch chip exhibits an SEE tolerance exceeding 75.8 MeV•cm2/mg, highlighting its potential to enhance the radiation tolerance of analog switches.

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