MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems

Chen, Di; Jin, Hai; Liao, Xiaofei; Liu, Haikun; Guo, Rentong; Liu, Dong

doi:10.23919/date.2017.7927151

Cited by 12 publications

(6 citation statements)

References 18 publications

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“…Some cache techniques [18]- [20] were suggested earlier for improving traditional average memory access time for multi-level cache systems. In [18], hardware prefetching was considered to exploit spatial and temporal locality of references.…”

Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

“…In [19], multi-level caches were considered as primary and secondary memories for proxy servers to access web content. In [20], an LRU replacement policy was proposed that makes use of the awareness of the cache miss-penalty to ensure memory access latency is balanced for memory system built with different memory technologies termed as "hybrid" system. The work addressed in [18]- [20] were specific cache techniques attempted to reduce average memory access time without considering any cost implications.…”

Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

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An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

Ramesh

Abed

2022

IJRES

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<p><span lang="EN-US">Many-core chip multiprocessor offers high parallel processing power for big data analytics; however, they require efficient multi-level cache and interconnection to achieve high system throughput. Using on-chip first level L1 and second level L2 per core fast private caches is expensive for large number of cores. In this paper, for moderate number of cores from 16 to 64, we present a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a cost-efficient geometrically bus-based interconnection. In our approach, we extracted cache hit and miss concurrencies and applied concurrent average memory access time to more accurately determine the cache system performance. We conducted least recently used cache policy-based simulation for cache system with L1, with L1/L2, and with L1/shared bus cache. Our simulation results show that an average system throughput improvement of 2.5x can be achieved by using system with L1/shared bus cache system compared to using only first level L1 or L1/L2. Further, we show that the throughput degradation for the proposed cache system is only within 5% for a single bus fault, suggesting a good bus fault tolerance.</span></p>

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Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

Ramesh

Abed

2022

IJRES

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“…To minimize energy consumption, the authors have proposed hybrid cache architecture composed of non-volatile memory (NVM) and DRAM. The MALRU (Misslatency Aware LRU) [28] cache replacement algorithm tries to retain NVM block (high latency) in memory and preferentially selects victim from the DRAM block (low latency). Simultaneously MALRU keep on updating the reserve section of DRAM blocks to improve the performance.…”

Section: Cost-based Replacement Algorithmsmentioning

confidence: 99%

A Categorical Study on Cache Replacement Policies for Hierarchical Cache Memory

Das

Roy

2020

Applications of Internet of Things

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Cache memory plays an important role in the in-memory computation in memory-intensive applications. Hierarchical cache design is used to increase the capacity of cache to handle large working set. The last level cache (LLC) does not strictly follow the temporal locality of program, so it becomes challenging to identify the blocks that will not be reused (dead block). In this paper, we have performed a detail survey on different techniques to detect the dead blocks early in the cache memory and improve the hit rate of cache replacement algorithm. Belady's optimal solution detects the dead block by analyzing the future of blocks, which is completely un-realistic. Many researches have been done to detect dead block practically by observing the previous access pattern. Many algorithms are proposed to improve the performance of traditional replacement policies by considering different additional information. Most of the algorithm aims to reduce the miss count by retaining the blocks that will be reused before eviction (live blocks). Recent study observes that the cost of all the cache miss are not uniform in nature. So, some researchers have distinguished between high-cost block and low-cost block. The overall cost can be reduced by retaining the high-cost block in memory, with little higher miss count. It is observed that by managing cache miss un-coordinately among the different levels of cache memory, it is not possible to obtain maximum utilization of memory. Many adaptive algorithms have been proposed to maintain balance between the over-utilized blocks and underutilized blocks by the displacement of blocks. In this survey, we have categorized the practically implemented techniques into different classes based on their basic principle of cache replacement.

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“…Some studies have proposed techniques for reducing the number of LLC writebacks to the nonvolatile component of a hybrid main memory consisting of NVM and DRAM [6,35]. In Reference [6], a miss penalty-aware LRU-based cache replacement policy, called MALRU is proposed to consider the asymmetry of cache miss penalty on DRAM and NVM. MALRU keeps the high-latency NVM blocks as well as the low-latency DRAM blocks with good temporal locality in a reserved area to protect them from being evicted.…”

Section: Related Workmentioning

confidence: 99%

Writeback-Aware LLC Management for PCM-Based Main Memory Systems

Pourshirazi

Beigi

Zhu

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

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With the increase in the number of data-intensive applications on today's workloads, DRAM-based main memories are struggling to satisfy the growing data demand capacity. Phase Change Memory (PCM) is a type of non-volatile memory technology that has been explored as a promising alternative for DRAM-based main memories due to its better scalability and lower leakage energy. Despite its many advantages, PCM also has shortcomings such as long write latency, high write energy consumption, and limited write endurance, which are all related to the write operations. In this article, we propose a novel writeback-aware Last Level Cache (LLC) management scheme named WALL to reduce the number of LLC writebacks and consequently improve performance, energy efficiency, and lifetime of a PCM-based main memory system. First, we investigate the writeback behavior of LLC sets and show that writebacks are not uniformly distributed among sets; some sets observe much higher writeback rates than others. We then propose a writeback-aware set-balancing mechanism, which employs the underutilized LLC sets with few writebacks as an auxiliary storage for the evicted dirty lines from sets with frequent writebacks. We also propose a simple and effective writeback-aware replacement policy to avoid the eviction of the dirty blocks that are highly reused after being evicted from the cache. Our experimental results show that WALL achieves an average of 30.9% reduction in the total number of LLC writebacks, compared to the baseline scheme, which uses the LRU replacement policy. As a result, WALL can reduce the memory energy consumption by 23.1% and enhance PCM lifetime by 1.29×, on average, on an 8-core system with a 4GB PCM main memory, running memory-intensive applications. CCS Concepts: • Computer systems organization → Processors and memory architectures; • Hardware → Emerging technologies;

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MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems

Cited by 12 publications

References 18 publications

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

A Categorical Study on Cache Replacement Policies for Hierarchical Cache Memory

Writeback-Aware LLC Management for PCM-Based Main Memory Systems

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