2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE) 2021
DOI: 10.23919/date51398.2021.9474026
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Malicious Routing: Circumventing Bitstream-level Verification for FPGAs

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Cited by 8 publications
(2 citation statements)
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“…3) Triggers: There are hardware Trojans exploiting don't care conditions for their trigger mechanisms [13], or data patterns in specific memory addresses [14], or even dedicated input images [15]. Some attacks have even more sophisticated triggers which are activated during the design flow, leaving no trigger signal to the possible detection algorithm [16,17].…”
Section: Hardware Trojansmentioning
confidence: 99%
See 1 more Smart Citation
“…3) Triggers: There are hardware Trojans exploiting don't care conditions for their trigger mechanisms [13], or data patterns in specific memory addresses [14], or even dedicated input images [15]. Some attacks have even more sophisticated triggers which are activated during the design flow, leaving no trigger signal to the possible detection algorithm [16,17].…”
Section: Hardware Trojansmentioning
confidence: 99%
“…6) Resources required: For the majority of the Trojans we study, the attacker needs knowledge of the design and access to it (e.g. bitstream [29], netlists [30] or access to the design tools [16,17,31]).…”
Section: Hardware Trojansmentioning
confidence: 99%