Making a Case for Partially Connected 3D NoC

Abstract

3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient manycore computing platforms. Two of the commonly used vertical interconnection technologies are: through silicon via (TSV) and near-field inductive coupling (NFIC). Both TSV- and NFIC-based links introduce additional area overhead. One of the possible ways to reduce the area overhead is to design partially connected 3D NoC with minimal effect on overall performance. The achievable performance of the partially connected 3D NoCs depends on the area, energy, and bandwidth of the vertical links. Moreover, the electromigration-induced failure of TSV is more severe than the misalignment-induced error in NFIC. By considering all these pertinent factors, we demonstrate that it is indeed possible to design a partially connected NFIC-based 3D NoC that performs as good as a fully connected TSV-based counterpart when the data rate is below a certain limit. For higher data rates, the partially connected TSV-based 3D NoC is a viable solution. However, NFIC-based 3D NoC is always more robust than the TSV-based counterpart.

AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs

“…Therefore, AdEle is evaluated using different elevator-placement patterns to show that its efficacy is independent of any such patterns. Also, because of performance-area trade-off in PC-3DNoCs [1], various elevator concentrations might be employed. Therefore, here we simulate different concentration of elevators to show that AdEle performance is not limited by elevator concentration.…”

“…Network-on-chip (NoC) has become the prevailing solution to enable scalable on-chip communication in manycore systems. Moreover, with the advances in three-dimensional (3D) integration technologies, 3D NoCs are emerging to further improve the heterogeneity and integration density by vertically stacking multiple dies connected with an efficient die-to-die interconnect [1]. Among different vertical interconnect technologies, through-silicon vias (TSVs) promise high bandwidth and low power [2]- [4].…”

“…Also, TSVs are particularly susceptible to electromigration and capacitive crosstalk-induced issues [8], [9]. Therefore, 3D NoC architectures with TSVs at every router (i.e., fully connected) impose higher design complexity, fabrication costs, and performance degradation [1], [4]. Addressing such challenges has motivated the development of 3D NoCs with fewer TSV-based vertical links, also known as partially connected 3D NoCs (PC-3DNoCs) [1], [10], [11].…”

“…In particular, the vertical links (a.k.a. the elevators) must be shared among multiple routers, potentially creating traffic hotspots at the elevators and increasing the network latency [1]. To balance the traffic at these hotspot elevators, an adaptive routing technique is needed to select lower utilized elevators without detouring far from the minimal path (i.e., elevator-selection problem).…”

Approximate Priority Hybrid 3DNoC Buffered-Bufferless Router

“…Two of the most common ways for implementing vertical links, namely through silicon via (TSV) [ 23 ] and near-field inductive coupling (NFIC), impose an area overhead and also introduce errors and failures, reducing yield. Therefore, designers often choose to reduce the number of vertical links, leading to irregular, partially connected 3D architectures [ 24 ] (not a full mesh). This includes the wireless vertical link 3D NoCs in [ 25 , 26 ].…”