Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware

Abstract

The architectural changes introduced with multicore CPUs have triggered a redesign of main-memory join algorithms. In the last few years, two diverging views have appeared. One approach advocates careful tailoring of the algorithm to the architectural parameters (cache sizes, TLB, and memory bandwidth). The other approach argues that modern hardware is good enough at hiding cache and TLB miss latencies and, consequently, the careful tailoring can be omitted without sacrificing performance. In this paper we demonstrate through experimental analysis of different algorithms and architectures that hardware still matters. Join algorithms that are hardware conscious perform better than hardware-oblivious approaches. The analysis and comparisons in the paper show that many of the claims regarding the behavior of join algorithms that have appeared in literature are due to selection effects (relative table sizes, tuple sizes, the underlying architecture, using sorted data, etc.) and are not supported by experiments run under different parameters settings. Through the analysis, we shed light on how modern hardware affects the implementation of data operators and provide the fastest implementation of radix join to date, reaching close to 200 million tuples per second.

Distributed join algorithms on thousands of cores

“…Comparing sort-merge and hash join algorithms has been the topic of recent work for joins on multi-core systems and efficient algorithms for both strategies have been proposed [1,3,4,5,9,27,30]. Kim et al [27] concluded that although modern hardware currently favors hash join algorithms, future processors with wider Single-InstructionMultiple-Data (SIMD) instructions would significantly speed up sort-merge joins.…”

“…As previous work [27,9,4,5,3], we investigate the join operation in isolation and do not materialize the output, i.e., we do not fetch additional data over the network after the join result has been computed. …”

“…Their implementation reaches a throughput of 160M tuples/second on 64 cores. Based on the ideas proposed by Manegold et al [30], Balkesen et al [4,5] developed and evaluated an efficient implementation of the radix hash join and report a maximum throughput of 750M tuples/second on 64 cores. The same authors compared sort-merge and hash joins [3], and concluded that despite wider SIMD vectors, the radix hash join still outperforms sort-merge based algorithms.…”

“…For the build-probe phase, we use the hash table implementation of Balkesen et al [4], which consists of a contiguous array of buckets and enables cache-friendly access.…”

TPC-H Analyzed: Hidden Messages and Lessons Learned from an Influential Benchmark

“…At the time of this writing, there is active academic debate on how to parallelize the join operator on many-core architectures, with multiple sophisticated algorithms being devised and tested [17]. We can assume that the current generation of industrial systems runs less-sophisticated algorithms, and presumably in the current state may not scale linearly on many-core architectures.…”