MAHA: A Program for Datapath Synthesis

Parker, Alice C.; Pizarro, Jorge T.; Mlinar, Mitch

doi:10.1109/dac.1986.1586129

Cited by 191 publications

(75 citation statements)

References 7 publications

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“…Many fundamental algorithms addressing these individual problems were also developed. For example, the list scheduling algorithm [1] and its variants are widely used to solve scheduling problems with resource constraints [71]; the force-directed scheduling algorithm developed in HAL [74] is able to optimize resource requirements under a performance constraint. The path-based scheduling algorithm in the Yorktown Silicon Compiler is useful to optimize performance with conditional branches [12].…”

Section: A Early Effortsmentioning

confidence: 99%

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Cong

Liu

Neuendorffer

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

632

272

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Abstract-Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR).

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Section: A Early Effortsmentioning

confidence: 99%

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Cong

Liu

Neuendorffer

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

632

272

View full text Add to dashboard Cite

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“…Application of the technique to the Maha [11] example is shown in Fig. 4 (directed arcs represent control dependencies and undirected lines correspond to data dependencies).…”

Section: A Speculative Execution Modelmentioning

confidence: 99%

Incorporating speculative execution in exact control-dependent scheduling

Radivojevic

Brewer

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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-This paper describes a symbolic formulation that allows incorporation of speculative operation execution (preexecution) in an exact control-dependent scheduling of arbitrary forward branching control/data paths. The technique provides a closed form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. To extract parallelism implicit in the input specification Boolean 'guard' functions are used to identify paths where operations have to be scheduled and the execution order of the conditionals is dynamically resolved. An efficient and systematic iterative construction method is presented along with benchmark results.

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“…We can join several operations with data dependencies in one cycle (chaining) [3], [4], [12], [15] or execute an operation which crosses more than one cycle (multicycle operation). A multicycle operation can be performed by either a pipelined [ 121 or nonpipelined function unit.…”

Section: Considerations In Data-path Synthesismentioning

confidence: 99%