Magnetoresistive random access memory operation error by thermally activated reversal (invited)

Abstract

The reliability in magnetoresistive random access memory (MRAM) write operation was investigated for both toggle and asteroid memory chips developed with 0.18μm CMOS process. Thermally activated magnetization reversal, being the dominant origin of the intrinsic write error, was studied theoretically and experimentally. For asteroid MRAM, the bit line or word line disturbing error on half selected bits was proved to have significant effect on the write operation margin, even in the ideal case free from bit-to-bit switching field distribution and the hysteresis loop shift. For toggle MRAM, on the other hand, the dominant origin of the error occurs for selected bits, although its impact is much smaller than in the case of asteroid MRAM. As was expected from the estimation based on the single domain model, more than 10mA operation margin with the error rate of <10−9, which is sufficiently small for semiconductor IC memory, was achieved for the toggle MRAM.

Significant reduction in writing field of toggle MRAMs using novel free layer structures

“…The writing field along the each writing line, at which all 120 MTJs could be switched by toggle writing, was 72 Oe for d FCL ¼ 4Å . That for d FCL ¼ 7Å was lower at 47 Oe while the writing margin was significantly larger in much smaller MTJs than those of previously published reports [4,5].…”

Non-volatile magnetic random access memories (MRAM)

“…When the field is removed the SF layer will orient itself along the bit easy axis, with the magnetization directions of the two ferromagnetic layers of the SF structure reversed compared to their initial orientation. The bit writing sequence now requires the sequential application of the fields created by the current lines with a time overlap of ≈ 5 ns [34]. In toggle writing it is only possible to reverse the initial SF free layer orientation.…”

Hybrid CMOS/Magnetic Memories (MRAMs) and Logic Circuits

“…In conventional MRAM architecture the writing time required for the alignment of the storage layer along the applied field is about 3-7 ns [54,55]. The TA-MRAM write cycle should match these values to be competitive compared to conventional magnetic field-induced switching MRAMs.…”