MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper

Xu, Biying; Zhu, Keren; Liu, Mingjie; Lin, Yibo; Li, Shaolan; Tang, Xiyuan; Sun, Nan; Pan, David Z.

doi:10.1109/iccad45719.2019.8942060

Cited by 52 publications

(10 citation statements)

References 41 publications

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“…Inspired by the need of parallel CAD algorithms, Pipeflow introduces a new task-parallel pipeline programming model for users to create a pipeline scheduling framework without data abstraction. We establish Pipeflow atop the open-source parallel task graph programming system, Taskflow [15], because it has been successfully adopted by many important CAD projects under the DARPA IDEA program [3,22,36]. In this section, we will first give a brief introduction about Taskflow and then dive into the technical details of Pipeflow.…”

Section: Pipeflowmentioning

confidence: 99%

“…We establish Pipeflow atop the open-source task graph programming system, Taskflow, developed by Huang et al [15], to leverage its powerful tasking infrastructure. As Taskflow is being used by several important research projects [3,22,36], building Pipeflow on top will not only benefit existing users but also allow us to gain timely feedback from the Taskflow community. We summarize our contributions as follows:…”

Section: Introductionmentioning

confidence: 99%

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Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++

Chiu¹,

Huang²,

Guo³

et al. 2022

Preprint

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Pipeline is a fundamental parallel programming pattern. Mainstream pipeline programming frameworks count on data abstractions to perform pipeline scheduling. This design is convenient for data-centric pipeline applications but inefficient for algorithms that only exploit task parallelism in pipeline. As a result, we introduce a new task-parallel pipeline programming framework called Pipeflow. Pipeflow does not design yet another data abstraction but focuses on the pipeline scheduling itself, enabling more efficient implementation of task-parallel pipeline algorithms than existing frameworks. We have evaluated Pipeflow on both micro-benchmarks and real-world applications. As an example, Pipeflow outperforms oneTBB 24% and 10% faster in a VLSI placement and a timing analysis workloads that adopt pipeline parallelism to speed up runtimes, respectively.

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Section: Pipeflowmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++

Chiu¹,

Huang²,

Guo³

et al. 2022

Preprint

Self Cite

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“…In addition to its applications in VLSI manufacturability and yield, which is the main scope of this work, ML has been infiltrating into almost all stages of the VLSI design cycle. At the circuit synthesis level, ML has been used for circuit modeling and optimization especially for analog and mixed signal designs [21]- [23].…”

Section: A Machine Learning In Edamentioning

confidence: 99%

Re-examining VLSI manufacturing and yield through the lens of deep learning

Alawieh

Pan

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…Second, open-source enables a path to ensure that reported results can be reproducible. The traction for open-source is evidenced not only through the efforts in ALIGN, but also in other notable efforts on analog layout [21], digital layout (including back-end infrastructure such as parasitic extraction on power delivery that is more broadly applicable to any other class of design [22].…”

Section: Working In An Open-source Environmentmentioning

confidence: 99%

ALIGN: A System for Automating Analog Layout

Dhar¹,

Kunal²,

Li³

et al. 2020

Preprint

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ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits.

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MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper

Cited by 52 publications

References 41 publications

Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++

Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++

Re-examining VLSI manufacturing and yield through the lens of deep learning

ALIGN: A System for Automating Analog Layout

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