Machine Learning Based Hardware Trojan Detection Using Electromagnetic Emanation

Takahashi, Junko; Okabe, Keiichi; Itoh, Hiroki; Ngo, Xuan Thuy; Guilley, Sylvain; Shrivastwa, Ritu Ranjan; Ahmed, Mushir; Lejoly, Patrick

doi:10.1007/978-3-030-61078-4_1

Cited by 1 publication

(1 citation statement)

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“…This results in an area overhead of 27% when using the Rocket BOOM RISC-V core. Takahashi et al [17] propose two detection methods based on machine learning and side-channel analysis. The methods were successful in detecting HWTs in PicoRV and Freedom RISC-V cores.…”

Section: Introductionmentioning

confidence: 99%

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

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et al. 2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.

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Section: Introductionmentioning

confidence: 99%