Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors

Abstract

In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors

“…0 to 0.65 conditions of the NSFET are similar to our previous paper [11]. First, we designed the NSFET device, and compared the electrical characteristics of the NSFET with published NSFET measurement data [15], and then design the NC-NSFET by replacing the ferroelectric (FE) material [16], [17], as shown in Fig.…”

“…Adam was used as the optimizer for the model training, and a learning rate scheduler was used to gradually decrease the learning rate during epochs. An MSEbased physics-augmented loss function was used as presented in the previous study [11]. Fig.…”

“…Therefore, it is necessary to adjust the appropriate number of layers and nodes according to the target accuracy and SPICE speed. Our previous study [11] demonstrated that the SPICE speed was faster than a state-of-the-art compact model. Unlike the previous work, which conducted model training through five structural parameters representing more than 98% of the device, in this paper, temperature and L CDD variables were newly added and model training was conducted with seven parameters.…”

“…It is known that a Verilog-A model is much slower than the BSIM-CMG model in simulation [13]. As shown in [11], a Verilog-A model is 5 to 6 times slower than the C-version model. Compared to the equivalent Verilog-A model, the ANN-based model is much simpler and faster than the BSIM-CMG model which is based on all the complex charge equations.…”

“…However, these methods cannot be applied until the compact model of a new device is developed. Therefore, research on generating SPICE models based on ML has been reported, including our papers [11]− [13]. SPICE models must reflect changes in transistor size and temperature and accurately respond to circuit performance based on the DC, AC, and transient simulations.…”