Machine Learning-Based Approach for Hardware Faults Prediction

Khalil, Kasem; Eldash, Omar; Kumar, Ashok; Bayoumi, Magdy

doi:10.1109/tcsi.2020.3010743

Cited by 71 publications

(19 citation statements)

References 29 publications

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“…Hardware failure detection is a common consideration for chip designers [24], however, they often do not consider an intended fault injected to the circuit. Many types of defenses have been proposed and tested against fault attacks.…”

Section: Countermeasuresmentioning

confidence: 99%

Practical, Low-Cost Fault Injection Attacks on Personal Smart Devices

Oren

2022

Applied Sciences

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Fault attacks are traditionally considered under a threat model that assumes the device under test is in the possession of the attacker. We propose a variation on this model. In our model, the attacker integrates a fault injection circuit into a malicious field-replaceable unit, or FRU, which is later placed by the victim in close proximity to their own device. Examples of devices which incorporate FRUs include interface cards in routers, touch screens and sensor assemblies in mobile phones, ink cartridges in printers, batteries in health sensors, and so on. FRUs are often installed by after-market repair technicians without properly verifying their authenticity, and previous works have shown they can be used as vectors for various attacks on the privacy and integrity of smart devices. We design and implement a low-cost fault injection circuit suitable for placement inside a malicious FRU, and show how it can be used to practically extract secrets from a privileged system process through a combined hardware-software approach, even if the attacker software application only has user-level permissions. Our prototype produces highly effective and repeatable attacks, despite its cost being several orders of magnitude less than that of commonly used fault injection analysis lab setups. This threat model allows fault attacks to be carried out remotely, even if the device under test is in the hands of the victim. Considered together with recent advances in software-only fault attacks, we argue that resistance to fault attacks should be built into additional classes of devices.

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Section: Countermeasuresmentioning

confidence: 99%

Practical, Low-Cost Fault Injection Attacks on Personal Smart Devices

Oren

2022

Applied Sciences

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“…In this paper, a convolution kernel with a series of wavelet structures is constructed based on the Daubechies wavelet to obtain multiple analysis results. We use the ability of wavelet analysis to mine the time-frequency domain features of the signal to obtain the effective associated fault features [24]. At the same time, gradient update learning is allowed.…”

Section: A Convolution Layermentioning

confidence: 99%

Research on a Rolling Bearing Fault Detection Method With Wavelet Convolution Deep Transfer Learning

2021

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“…In actual use, the errors of memory in online occur due to various causes such as the aging of elements [36], the failure of modules in memory [37]. When correcting data of the memory in online, regardless of the cause of the error, it is recognized as an error in the memory cell and corrected by ECC.…”

Section: Reliabilitymentioning

confidence: 99%

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

Han

Lee

et al. 2021

IEEE Access

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Advanced capacity and density of memory have resulted in an increase in the probability of memory faults. The in-memory Error Correction Code (ECC), which solves this problem, is a widely used technology to improve the yield of highly integrated memory. However, the use of in-memory ECC causes problems that have not been considered in memory repair algorithms. Redundancy analysis is effective for repairing memory with redundant memory and in-memory ECC. In this paper, an ECC-aware fast and reliable pattern matching redundancy analysis algorithm for memory using both spare memory and in-memory ECC is proposed. This algorithm simplifies large-scale fault groups using in-memory ECC and includes an early termination method that can determine whether a memory that cannot be repaired with line spares can be repaired considering in-memory ECC. Experimental results show that the proposed pattern matching redundancy analysis algorithm achieves a similar yield but 14.6% less RA time and 8.6 times higher reliability compared to the existing redundancy analysis algorithms.

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Machine Learning-Based Approach for Hardware Faults Prediction

Cited by 71 publications

References 29 publications

Practical, Low-Cost Fault Injection Attacks on Personal Smart Devices

Practical, Low-Cost Fault Injection Attacks on Personal Smart Devices

Research on a Rolling Bearing Fault Detection Method With Wavelet Convolution Deep Transfer Learning

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

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