LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR

Zhu, Yihong; Zhu, Min; Yang, Bohan; Zhu, Wenping; Deng, Chenchen; Chen, Chen; Wei, Shaojun; Liu, Leibo

doi:10.1109/tcsi.2020.3048395

Cited by 50 publications

(37 citation statements)

References 17 publications

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“…At the submission time of this paper, our architectures generated using HLS lead to comparable, and sometimes better, results compared to the best references from the state of the art using HDL (such as [20], [19], [31], [25]) but probably for a much smaller design effort. Recent HDL based solutions (such as [36], [35]) are faster and smaller than ours. We showed how HLS can be used effectively to parallelize implementations.…”

Section: Discussionmentioning

confidence: 83%

Lattice-based Cryptosystems on FPGA: Parallelization and Comparison using HLS

Zijlstra¹,

Bigou²,

Tisserand³

2021

IEEE Trans. Comput.

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This paper deals with hardware implementations for lattice-based cryptography. Various CPA and CCA secure algorithms for LWE, RLWE and MLWE problems have been studied, parallelized, implemented and compared on FPGA using high-level synthesis. The impact of PRNG choices on the implementations performances and costs is also evaluated. HLS allows us to compare various sets of algorithms, architectures and parameters with a reduced design effort. Our results are often similar to state-of-the-art for various speed and cost trade-offs. Sometimes we obtain better results thanks to the exploration of numerous architecture and algorithm optimizations.

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Section: Discussionmentioning

confidence: 83%

Lattice-based Cryptosystems on FPGA: Parallelization and Comparison using HLS

Zijlstra¹,

Bigou²,

Tisserand³

2021

IEEE Trans. Comput.

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“…Several hardware accelerators for the lattice-based cryptography without using the NTT algorithm have been proposed recently [6], [17], [18], [31], [32], [33], [34], [35]. As expected, optimizing the polynomial multiplier is the main focus of these works, since it is the bottleneck.…”

Section: Prior Hardware Implementationsmentioning

confidence: 99%

“…This architecture requires fewer post-processing operations than the Karatsuba algorithm [16]. The experimental result shows that the proposed fast 4-parallel architecture has the lowest actual latency compared with prior works [6], [17], [18].…”

Section: Introductionmentioning

confidence: 99%

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography

Tan¹,

Wang²,

Lao³

et al. 2021

Preprint

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This paper presents a low-latency hardware accelerator for modular polynomial multiplication for lattice-based post-quantum cryptography and homomorphic encryption applications. The proposed novel modular polynomial multiplier exploits the fast finite impulse response (FIR) filter architecture to reduce the computational complexity for the schoolbook modular polynomial multiplication. We also extend this structure to fast M -parallel architectures while achieving low-latency, high-speed, and full hardware utilization. We comprehensively evaluate the performance of the proposed architectures under various polynomial settings as well as in the Saber scheme for post-quantum cryptography as a case study. The experimental results show that our design reduces the computational time and area-time product by 61% and 32%, respectively, compared to the state-of-the-art designs.

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“…2 along with the complete architecture. Since Saber needs the final result C(x) to be reduced by It should be noted that previous implementations as of now are either for LWE based scheme [5], or post silicon is not verified [6], [7]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Key generation, encapsulation and decapsulation consume 444.1, 579.4 & 724.5 uJ energy for entire operation in the above-mentioned operating point. A comparison table with other state-of-the-art implementations [5], [6], [7] (LWE based) is presented in Fig. 6.…”

Section: Introductionmentioning

confidence: 99%

A 333.9uW 0.158mm$^2$ Saber Learning with Rounding based Post-Quantum Crypto Accelerator

Ghosh¹,

Mera²,

Karmakar³

et al. 2022

Preprint

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Institute of Standard & Technology (NIST)is currently running a multiyearlong standardization procedure to select quantumsafe or postquantum cryptographic schemes to be used in the future. Saber is the only LWR based algorithm to be in the final of Round 3. This work presents a Saber ASIC which provides 1.37X power-efficient, 1.75× lower area, and 4× less memory implementation w.r.t. other SoA PQC ASIC. The energyhungry multiplier block is 1.5× energyefficient than SoA.

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LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR

Cited by 50 publications

References 17 publications

Lattice-based Cryptosystems on FPGA: Parallelization and Comparison using HLS

Lattice-based Cryptosystems on FPGA: Parallelization and Comparison using HLS

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography

A 333.9uW 0.158mm$^2$ Saber Learning with Rounding based Post-Quantum Crypto Accelerator

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