LUT Optimization Using APC and OMS Techniques

Abstract

Recently, we have proposed the anti symmetric product coding (APC) and odd-multiple-storage (OMS) techniques for lookup-table (LUT) design for memory-based multipliers to be used in digital signal processing applications. Each of these techniques results in the reduction of the LUT size by a factor of two. In this brief, we present a different form of APC and a modified OMS scheme, in order to combine them for efficient memory-based multiplication. The proposed combined approach provides a reduction in LUT size to one-fourth of the conventional LUT. We have also suggested a simple technique for selective sign reversal to be used in the proposed design. It is shown that the proposed LUT design for small input sizes can be used for efficient implementation of high-precision multiplication by input operand decomposition. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD)-based multipliers. For 16-and 32-bit word sizes, respectively, it offers more than 30% and 50% of saving in area-delay product over the corresponding CSD multipliers. Keywords: Digital signal processing (DSP) chip, lookup-table (LUT)-based computing, memory-based computing, very large scale integration (VLSI). I. INTRODUCTIONRegistering with memory stages are regularly used to give the advantage of equipment reconfigurability. Reconfigurable figuring stages offer points of interest as far as lessened plan cost, early time-to-market, fast prototyping and effortlessly adaptable equipment frameworks. Duplication in twofold is like its decimal partner. Two numbers A and B can be duplicated by halfway items: for every digit in B, the result of that digit in A is computed and composed on another line, moved leftward so that its furthest right digit lines up with the digit in B that was utilized. The whole of all these fractional items gives the last outcome. Delicate multipliers area to a great degree adaptable other option to utilizing DSP squares. Rather than actualizing a combinatorial rationale multiplier, they use a novel execution in view of a fractional look-into table (LUT) usage of the increase operation, where the LUT is executed in the memory squares. Delicate multipliers increment by an element of in the vicinity of 2 and 15 the quantity of multipliers accessible. By downloading distinctive coefficient LUTs, diverse setups of multipliers and adders are created. An ordinary query table (LUT) -based multiplier is appeared in underneath figure, where A will be a settled coefficient, and X is an information word to be increased with A. Accepting X to be a positive double number of word length L, there can be 2L conceivable estimations of X, and in like manner, there can be 2L conceivable estimations of item C = A • X.