LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level

Moy, Matthieu; Maraninchi, Florence; Maillet-Contoz, Laurent

doi:10.1007/s10617-006-9044-6

Cited by 38 publications

(28 citation statements)

References 22 publications

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“…Tabakov et al conclude that the state of the kernel must be exposed to a certain extent, in order to enable the user to specify properties at different temporal resolutions. Moy et al [15], [16] also proposed exposing information from the kernel, but their abstraction is motivated by the types of properties they want to check while Tabakov et al argue that the abstraction should expose fully SystemC's simulation semantics, as described in [1]. A coarse abstraction might hide details that may be of importance to some users.…”

Section: A Exposing the Simulation Semanticsmentioning

confidence: 99%

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Monitoring temporal SystemC properties

Tabakov¹,

Vardi²

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

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Abstract-Monitoring temporal SystemC properties is crucial for the validation of functional and transaction-level models, yet the current SystemC standard provides no support for temporal specifications. In this work we describe a temporal monitoring framework for the SystemC specification language defined by Tabakov et al. at FMCAD'08. Our framework uses a very minimal modification of the SystemC kernel, exposing event notifications and simulation phases. The user code is instrumented to allow observation of the relevant parts of the model state. As proof of concept, we use the framework to specify and check properties of two SystemC models. We show that monitoring SystemC properties using this framework has reasonable overhead (0.01% -1%) and has decreasing marginal cost. Finally, we demonstrate that monitoring at different levels of abstraction requires very small changes to the specification and the generated monitors. Based on our empirical results we argue that the additional expressive powers and flexibility of the framework does not incur a serious performance hit.

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Section: A Exposing the Simulation Semanticsmentioning

confidence: 99%

“…For example, algorithmic-level SystemC models are often timeless, with the simulation being completely driven by events and the simulation clock making no progress during the whole simulation [9], [15]. In fact, the whole simulation can consist of a single delta cycle, if the simulation is driven solely by immediate event notifications.…”

Section: (4)mentioning

confidence: 99%

Monitoring temporal SystemC properties

Tabakov¹,

Vardi²

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

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“…However, the design entry of this method is UML and only during the construction of the derived FSM some properties can be checked. Another approach has been proposed in [9]. A formal model can be extracted in terms of communicating state machines and can be translated into an input language for several verification tools.…”

Section: Related Workmentioning

confidence: 99%

Proving transaction and system-level properties of untimed SystemC TLM designs

Große

Drechsler

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

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Abstract-Electronic System Level (ESL) design manages the enormous complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for describing complex communication without all the details. As ESL language, SystemC has become the de facto standard. Since the SystemC TLM models are used for early software development and as reference for hardware implementation their correct functional behavior is crucial. Admittedly, the best possible verification quality can be achieved with formal approaches. However, formal verification of TLM models is a hard task. Existing methods basically consider local properties or have extremely high run-time. In contrast, the approach proposed in this paper can verify "true" TLM properties, i.e. major TLM behavior like for instance the effect of a transaction and that the transaction is only started after a certain event can be proven.Our approach works as follows: After a fully automatic SystemC-to-C transformation, the TLM property is mapped to monitoring logic using C assertions and finite state machines. To detect a violation of the property the approach uses a BMC-based formulation over the outermost loop of the SystemC scheduler. In addition, we improve this verification method significantly by employing induction on the C model forming a complete and efficient approach. As shown by experiments state-of-the-art proof techniques allow proving important non-trivial behavior of SystemC TLM designs.

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“…Like our approach, most of these translations are manually, a notable exception being the LusSy tool chain [13], which automatically translates TLM models into synchronous automata with variables; it provides some simple abstraction techniques (e.g., abstract address representation). The LusSy tool chain has been connected to many model checkers, including symbolic model checkers based on BDD or SAT.…”

Section: Translation-based Approachesmentioning

confidence: 99%

Verification of an industrial SystemC/TLM model using LOTOS and CADP

Garavel

Helmstetter

Ponsini

et al. 2009

2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design

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SystemC/TLM is a widely used standard for system level descriptions of complex architectures. It is particularly useful for fast simulation, thus allowing early development and testing of the targeted software. In general, formal verification of SystemC/TLM relies on the translation of the complete model into a language accepted by a verification tool. In this paper, we present an approach to the validation of a SystemC/TLM description by translation into LOTOS, reusing as much as possible of the original SystemC/TLM C++ code. To this end, we exploit a feature offered by the formal verification toolbox CADP, namely the import of external C code in a LOTOS model. We report on experiments of our approach on the BDisp, a complex graphical processing unit designed by STMicroelectronics.

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LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level

Cited by 38 publications

References 22 publications

Monitoring temporal SystemC properties

Monitoring temporal SystemC properties

Proving transaction and system-level properties of untimed SystemC TLM designs

Verification of an industrial SystemC/TLM model using LOTOS and CADP

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