LTE layer 1 software design on multicore DSP architectures

Garg, Umang; Brogioli, Michael C.; Gaur, Vatsal; Jain, Naresh C.; Irudayaraj, Arokia

doi:10.1109/acssc.2011.6190139

Cited by 2 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For the first 4 cores of each chip on the board, the route information is as in Table . The first 4 channels are used for inter-core IPC. For the LTE coordinated multipoint (CoMP) feature, the channel estimation (CE) [13] task of one chip need to send its CE result to the other two chips. Channel 5, 6 and 7 are used for this inter-chip IPC.…”

Section: The Commn Ipc Designmentioning

confidence: 99%

A High Efficient Common IPC for LTE Layer1 Multi-core DSP/SoC System

Xiang

Jiang

Shang

2014

2014 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery

View full text Add to dashboard Cite

Multi-core digital signal processor (DSP) and system on chip (SoC) are widely used in LTE baseband these years. A companion paper (Hao Xiang et at., 2013) [1] presented a kind of 3 layers multi-core DSP/SoC software architecture, and mentioned the common IPC is the key for this flexible architecture. This common IPC is detailed in this paper. LTE system has hundreds of configurations from different antenna numbers, bandwidth andDownlink Uplink ratios combinations. The taskcore mapping should always be updated according to different configuration scenario. However, this update will seriously impact the software architecture, if the task-core mapping is visible to the architecture. This paper presents a shared memory based IPC. It automatically adapts to the different task-core mapping scenarios, provides a common and transparent IPC channel to the upper layers. Based on this common IPC, each task can be flexibly mapped to any core dynamically. And this dynamic mapping is transparent to the upper layers, so it hasn't impact on the software architecture any more. This paper makes several contributions to the common IPC development. The first one is the shared memory self-healing circular buffer design. This shared memory based design supports zerocopy, so as to improve the IPC efficiency. This design also supports self-check and self-recovery, so as to achieve the self-healing reliability. The second one is the inter-core N senders -1 receiver IPC channel design. The third one is the IPC commonizing and optimization for multi-core system. Our evaluation shows the advantages of this common IPC. 1) It is common and transparent to upper layers, so it supports the flexibly task-core mapping. 2) It is a high efficient IPC. After the optimization, in the 256 bytes message inter-core IPC case, it is 4.5 times faster than the same IPC in SmartOS.

show abstract

Section: The Commn Ipc Designmentioning

confidence: 99%

A High Efficient Common IPC for LTE Layer1 Multi-core DSP/SoC System

Xiang

Jiang

Shang

2014

2014 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery

View full text Add to dashboard Cite

show abstract

“…In [11], a traditional 3 layers architecture is reported: accelerators driver layer, OS layer and application layer. In [12], a similar architecture is proposed.…”

Section: Introductionmentioning

confidence: 99%

A new multi-core software architecture for improving CUR in LTE Layer1 DSP/SoC

Xiang

Yang²,

Zheng³

et al. 2013

2013 International Conference on Connected Vehicles and Expo (ICCVE)

View full text Add to dashboard Cite

Multi-core digital signal processor (DSP) and system on chip (SoC) are widely used in Long Term Evolution (LTE) L1 development since 5 years ago. The corresponding multi-core software architecture design is a big challenge. Nowadays, a traditional 3 layers architecture is very popular. Its 3 layers are accelerators driver layer, OS layer and application layer. One shortage of this architecture is the weak cross-vendor portability. A worse one is the low chip capability utilization rate (CUR) in some cases.In order to improve the CUR and simplify the cross-vendor porting, an improved hierarchy architecture is presented in this paper. Its 3 layers are different from the above traditional ones: the operating system (OS) layer, control process layer and user process layer. In this proposed new architecture, an InterProcess Communication (IPC) module is newly developed and added into OS layer. Above the OS, the user process is separated from the control process. The global buffers are the bridges between these two layers, and could be cross-core shared by both control process and user process tasks. The common IPC supports transparent and flexible communication between all tasks on all cores. As a result, tasks can be dynamically mapped on cores at run time. Based on the LTE projects practice, three improvements are obtained with this new architecture. 1) All the user process tasks can be flexibly scheduled among cores. The core load can be balanced very well in each scenario, so as to improve the CUR. 2) Almost all the control process tasks ( in C language ) can be directly reused on other venders' DSP/SoC. The cross-vendor porting is simplified. 3) All layers can be developed in parallel to speed up the time to market (TTM) progress.

show abstract

LTE layer 1 software design on multicore DSP architectures

Cited by 2 publications

References 0 publications

A High Efficient Common IPC for LTE Layer1 Multi-core DSP/SoC System

A High Efficient Common IPC for LTE Layer1 Multi-core DSP/SoC System

A new multi-core software architecture for improving CUR in LTE Layer1 DSP/SoC

Contact Info

Product

Resources

About