High performance signal processing for digital video signals needs parallelism of processing elements (PES) [ 1,2]. The WSI approach allows for a fast clocked system arrangement of redundant bus-connected PE parts, configurable towards a multi-PE by -among other facilities-the use of laser processing for connections/disconnections [3,41. To demonstrate the configuration procedure and system principle on silicon samples, a CADsimulation and layout environment was established at the Philips Components ASIC Centre Hamburg. The design flow, described in this paper, includes standard tools and project-specific extensions, especially for verification tasks and preparation of WSI data fractioning. The factory interface, packaging and pretest flow was developed in close cooperation between philips, Hamburg, and European Silicon Structures, Rousset. Fabrication of 5-inch wafers with about three 16 sqcm units per wafer is scheduled for the end of 1990. This paper aims at the description of questions and solutions to pragmatic problems within the scope of WSI silicon realizations and packaging tasks under the constraints of cost efficient and time efficient standardized ASIC flows.