<title>Teramac configurable custom computer</title>

Exploring architectures for volume visualization on the Teramac custom computer

“…See figure 5. For each point in a 256 3 volume, Teramac computes a set of cylindrical convolutions to sample the range of all possible orientations and artery diameters, centered at the point. The maximum convolution in the set computed for each point is found and its value, orientation, and diameter are saved.…”

“…During the last year, we have had the experience of putting a number of large applications on the Teramac Custom Computer [1,2,3]. Teramac is a modern bread-board for the VLSI age; it was designed to facilitate architectural experimentation by allowing designs to be quickly implemented and quickly executed, which in turn allows many design-and-test iterations to be performed in a short time.…”

Unifying simulation and execution in a design environment for FPGA systems

“…Splash2 [1] and DecPerle-1 [2] could use readback (readback is the ability of Xilinx FPGAs to dump the internal state of memory elements as a user-accessible bitstream) to access the internal FPGA state and could match this state with some of the symbolic signal names found in the original design specification. Teramac [3] and DecPerle-1 both had rudimentary breakpoint capabilities that allowed the designer to define a single hardware event that could be used to stop the global system clock. Finally, the work described in [4] allowed a Verilog simulator to request a hardware readback and could then display the retrieved flip flop values in a table.…”

“…However, users typically clock the hardware thousands or millions of clock cycles before acquiring the FPGA state; the hardware debugger can be easily over 10 0002 faster than simulation in these cases 3. It is usually only feasible to retrieve data from FPGA state elements, intermediate combinational signals are not available.…”