&lt;title&gt;Run-time reconfigurable 2D discrete wavelet transform using JBits&lt;/title&gt;

Ballagh, Jonathan; Athanas, Peter; Keller, Eric

doi:10.1117/12.434374

Cited by 4 publications

(5 citation statements)

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“…These scales are chosen as powers of 2 to use the discrete wavelet transform (DWT). The DWT can be easily implemented in digital processors and FPGAs [15]. The optimum features are selected using the following equations:…”

Section: Feature Selectionmentioning

confidence: 99%

Digital discrimination of neutrons and gamma-rays in liquid scintillators using wavelets

Yousefi

Lucchese

Aspinall

2009

Nuclear Instruments and Methods in Physics Research Section A:

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Section: Feature Selectionmentioning

confidence: 99%

Digital discrimination of neutrons and gamma-rays in liquid scintillators using wavelets

Yousefi

Lucchese

Aspinall

2009

Nuclear Instruments and Methods in Physics Research Section A:

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“…Such architectures allow the implementation of complex algorithms. A number of different techniques for implementing the discrete wavelet transform (DWT) in FPGAs exist in literature [10][11][12][13][14][15]28 including the implementation of MPEG-4 wavelet based visual texture compression system. 29 Recently, the lifting scheme 30-32 is introduced for real-time DWT 14,17 as well as the VLSI implementation of DWT using embedded instruction codes for symmetric filters.…”

Section: The Pipelined Fpga Implementation Of the Non-decimated Wavelmentioning

confidence: 99%

<title>Real-time wavelet domain video denoising implemented in FPGA</title>

et al. 2004

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In this paper we develop an advanced spatio-temporal wavelet domain filtering algorithm which is suitable for hardware implementation, we implement it in the Field Programmable Gate Arrays (FPGA) and report the results of real-time processing.The wavelet decomposition in our implementation is non-decimated with three decomposition levels and with a Daubechies' minimum phase orthogonal wavelet. Noise reduction is implemented with spatially adaptive Bayesian wavelet shrinkage. In the next filtering stage, a motion detector controls selective, recursive averaging of pixel intensities over time. The algorithm is customized for the hardware implementation and is realized in FPGA. The standard composite television video stream is digitalized and used as source for real-time video sequences. The results demonstrate the effectiveness of the developed scheme for real time video processing.

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“…Most of the resources of the FPGA, for instance, the configurable logic blocks (CLBs), routing switches and multiplexers, and input-output blocks (IOBs) can be accessed and configured by using JBits method calls. JBits method calls perform modifications to the FPGA at a very low level [13] and consequently developing a large application with such calls can be more difficult than using a highlevel hardware description language (HDL).…”

Section: Introductionmentioning

confidence: 99%

“…A core is a predesigned logic module that removes the need to implement an entire design in low-level detail [11]. While low-level elements can also be represented by a core, for instance an AND gate, the JBits RTP core specification provides a means for the design to be completed at a level of abstraction similar to that of traditional HDLs [13]. The difference between a JBits RTP core and cores used in traditional structural HDLs is that each JBits core must be physically placed and interconnected within the FPGA during implementation [13].…”

Section: Introductionmentioning

confidence: 99%

“…While low-level elements can also be represented by a core, for instance an AND gate, the JBits RTP core specification provides a means for the design to be completed at a level of abstraction similar to that of traditional HDLs [13]. The difference between a JBits RTP core and cores used in traditional structural HDLs is that each JBits core must be physically placed and interconnected within the FPGA during implementation [13]. JBits provides means to place the cores relative to other cores or by explicitly defining the coordinates of the core within the FPGA.…”

Section: Introductionmentioning

confidence: 99%

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A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs

Carreira

Fox

Turner

2003

EURASIP J. Adv. Signal Process.

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Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with a new application-specific mapping and placement method that uses JBits to avoid conventional general-purpose mapping and placement tools. JBits is a set of Java classes that provide an interface into the Xilinx Virtex FPGA configuration bitstream, allowing the user to generate new configuration bitstreams. PCLS coefficient generation allows passband-to-stopband energy ratio (PSR) performance to be traded for a reduction in the filter's hardware cost without altering the minimum stopband attenuation. Fixed-point coefficients that meet the frequency response and hardware cost specifications can be generated with the PCLS method. It is not possible to meet these specifications solely by the quantization of floating-point coefficients generated in other methods

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<title>Run-time reconfigurable 2D discrete wavelet transform using JBits</title>

Cited by 4 publications

References 0 publications

Digital discrimination of neutrons and gamma-rays in liquid scintillators using wavelets

Digital discrimination of neutrons and gamma-rays in liquid scintillators using wavelets

<title>Real-time wavelet domain video denoising implemented in FPGA</title>

A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs

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