<title>Nonlinear dynamical systems analyzer</title>

Abstract

Computationally intensive algorithms are an ever more common requirement ofmodem signal processing. Following the work ofGentleman and Kung, McWhirter, Shepherd and Proudler suggested that certain matrix-orientated algorithms can be mapped onto systolic array architectures for adaptive linear signal processing. This has been extended by Broomhead et a!. to the calculation of nonlinear predictive models and applied by Jones et al.to target identification and recognition. We shall showthat predictive models are extremely sharp discriminators. Our chosen problem, if implemented as a systolic array, would require 3403 processors which would result in high through-put rate at excessive cost. We are developing an efficient sub-optimally implemented systolic array; one processor servicing more than one systolic node.We describe a prototype Heuristic Processor which computes a multi-dimensional, nonlinear, predictive model. It consists of a Radial Basis Function Network and a least squares optimiser using QR decomposition. The optimised solution ofa set ofsimultaneous equations in 81 unknos is calculated in l5OpS. The QR section emulates a triangular systolic array by the novel use of an array of 40 mature silicon DSP chips costing under $100 each. The DSP chips operate in synchronism at a 50MHz clock rate passing data to each other through multi-port memories on a dead-letter box principle; there are no memory access conflicts and only two-port and three-port memories are required. The processor provides 1-GFlop of computing power per cubic-foot of electronics for a component cost of approximately $15,000.