&lt;title&gt;New cost-effective VLSI implementation of 2D discrete cosine transform and its inverse&lt;/title&gt;

Gong, Danian; He, Yun

doi:10.1117/12.411808

Cited by 2 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Preliminary evaluations show that the datapaths V and IV show more than twice the operating speeds compared to previous designs when mapped on the Virtex 5, and respectively provide 19-26% reduction in gate count. It is worth noting that the datapaths IV and V provide almost 3-4 times the throughput of dedicated DCT cores proposed by Gong et al [7] and Ruiz et al [8]. This has been achieved, as can be observed by simple yet important extensions to the previous designs.…”

Section: Performance Resultsmentioning

confidence: 72%

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices

Purohit

Chalamalasetti

Margala

et al. 2008

2008 International Conference on Reconfigurable Computing and FPGAs

View full text Add to dashboard Cite

This paper presents new power efficient high throughput datapaths for portable multimedia devices. The various datapaths provide support for dense arithmetic operations. This work provides the performance evaluation for a library of reconfigurable datapath elements (Processing Elements) previously proposed and presents two new processing element architectures to be part of power efficient portable, multimedia processing systems. The performance results show that the proposed designs will provide a higher efficiency in power and area consumption compared to the previously suggested and commercial solutions, and could prove highly beneficial for the target domain of multimedia operations on portable systems.

show abstract

Section: Performance Resultsmentioning

confidence: 72%

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices

Purohit

Chalamalasetti

Margala

et al. 2008

2008 International Conference on Reconfigurable Computing and FPGAs

View full text Add to dashboard Cite

show abstract

A single-chip real-time programmable video signal processor

Gong

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

View full text Add to dashboard Cite

In this paper, we describe a cost-efficient programmable video signal processor (PVSP) to implement various video encoding and decoding schemes. Hierarchical (two levels) programmable control architecture, flexible memory address mapping strategies and a p r o g m a b l e VLCNLD module are applied in order to achieve sufficient programmability. Thus, PVSP can support various video compression algorithms and standards, such as MPEG-1, MPEG-2 H.263, and MPEG-4. Meanwhile, to improve the throughput of this codec system, some paralleling approaches are exploited on different levels, which include pipeline, tree adder, and SIMD (single instruction stream, multiple data streams). PVSP is estimated to have approximately 320k gates and it can accomplish MPEG-2 MP@ML encoding in real-time at the frequency of 133MHz.

show abstract

<title>New cost-effective VLSI implementation of 2D discrete cosine transform and its inverse</title>

Cited by 2 publications

References 0 publications

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices

A single-chip real-time programmable video signal processor

Contact Info

Product

Resources

About