Nowadays, imagers based on CMOS active pixel sensors (APS) have performances that are competitive with those based on charge-coupled devices (CCD). CMOS imagers offer advantages in on-chip functionalities, system power reduction, cost and miniaturisation. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, we present the second version of FAMOSI which makes up for the drawbacks of the first one. FAMOSI 2 has a new architecture of pixel which implements an electronic shutter and analogue accumulation capabilities. With this kind of pixel and the new architecture for controlling the integration, FAMOSI 2 can work in the low power repetitive synchroscan mode. The prototype has been fabricated in the AMS 0.35µm CMOS process. The chip is composed of 64 columns per 64 rows of pixels. The pixels have a size of 20µm per 20µm and a fill factor of 47%.The simulation shows that a conversion gain of 3.4µV/e -is obtained with a dynamic range of 1.2V, a time resolution of 400ps and a light pulse repetitive rate of 300kHz.