High read-out noise has been the primary limitation to the performance of charge injection device (CID) image sensors. This is due to the inherent high read-out node capacitance of the conventional OlD image sensor architecture. In a conventional row read-out CID image sensor architecture, all rows of the pixel array are connected to a multiplexer. An output amplifier is integrated at the output of the multiplexer. The read-out node capacitance is the combination of the row and the multiplexer buses capacitances. This read-out node capacitance is in the order of magnitude of few to several pF, which yields an rms read-out-noise in the order of several hunderds to a thousand electrons. The pre-amplifier per row (PPR) architecture was introduced to reduce the readout node capacitance and consequently the read-out noise. In this architecture, an amplifier is dedicated to and integrated at the end of each row of the pixel array. The row bus is de-coupled from the multiplexer bus and the read-out node capacitance is reduced to that of the row bus. This read-out node capacitance is in the order of magnitude of one pF, which yields an rms readout noise in the order of few hunderds electrons.In this paper, a new OlD image sensor architecture, pre-amplifier per pixel (PPP), will be presented. In this architecture, an amplifier is dedicated to and integrated within each pixel of the image sensor array. The read-out node for a pixel design employing this architecture is local to its pixel and buffered from any other read-out nodes within the image sensor pixel array. Thus, the capacitance of the read-out node in this design is significantly reduced, resulting in significant improvements of read-out sensitivity and noise. This architecture reduces the read-out node capacitance to an order of magnitude of few tens of fF, which yields an rms read-out noise in the order of few tens of electrons. This brings the CID imaging technology to the main stream of readout noise levels of other solid-state imaging technologies. This is achieved without compromising the traditional strengths of CID imaging technology such as non-destructive read-out, resistance to blooming, radiation hardness, and random-accessibility. The only compromise is the pixel fill-factor. Depending on the minimum process feature size and the pixel size, the pixel fill-factor can be higher than 50%. A test chip has been designed and fabricated. Evaluation of this test chip is presented. 292 / SP1E Vol. 2415 O-8194-1762-9/95/$6.OO Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/20/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx