&lt;title&gt;Chip-level line-width prediction methodology&lt;/title&gt;

LaCour, Pat; Sahouria, Emile; Granik, Yuri

doi:10.1117/12.475669

Cited by 2 publications

(3 citation statements)

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“…As has been mentioned several times, the algorithm finally chosen for tapeout required some iteration of applied OPC with predicted results, using ORC and DRC (for more details refer to [3]). This combination has the significant A B…”

Section: Simulation and Drc Of Final Opcmentioning

confidence: 99%

<title>Model-based OPC for sub-resolution assist feature enhanced layouts</title>

et al. 2002

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Sub-resolution assist features (SRAF) have been demonstrated to provide significant process window improvement when used in combination with off-axis illumination (OAI) and attenuated phase shifted mask enhanced lithography ("attPSM"). While some through pitch linewidth variations can be reduced through the use of SRAF, the main goal is to improve common process window, leaving the task of linewidth control to conventional optical proximity correction (OPC). OPC in combination with SRAF is also required to address two-dimensional patterning infidelities such as corner rounding and line end shortening, for which SRAF do not provide adequate correction. Finally, OPC will be used as a means of recovering process window that may be lost in layout situations that result in poor SRAF coverage. With an industry wide migration from rules-based OPC to iterative, model-based solutions, the integration of inherently rules based SRAF generation and model-based OPC has to be investigated.

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Section: Simulation and Drc Of Final Opcmentioning

confidence: 99%

<title>Model-based OPC for sub-resolution assist feature enhanced layouts</title>

et al. 2002

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“…The technique also differentiates itself from the method of generation of a predicted CD contour of the simulated layer mentioned in Pat's paper [1] . In order to simplify the coding, we used the common TCL (Tool Control Language) in the Calibre OPC/ORC environment.…”

Section: Introuctionmentioning

confidence: 96%

“…Developing efficient and fast algorithm with capabilities of model-based gate CD calculation and analysis is the key to successful and fast implementation of the model-based full chip gate CD verification. Previous works [1][2] [3] have been reported for full chip CD related simulation or prediction. However only limited CD targets have been described in the * vincentshu@charteredsemi.com, ysshu2002@yahoo.com phone 65 6360 1767…”

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confidence: 99%

Full chip gate CD error prediction for model-based OPC

Shu¹,

Choi²,

Quek³

2005

Design and Process Integration for Microelectronic Manufacturing III

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In this paper, a technique for full chip gate CD(critical dimension) error prediction based on empirical models will be presented and discussed. In order to be compatible with existing common terminologies, this technique can also be called model-based full chip gate CD verification, which has become an integral part of closed-loop design-to-silicon flow of gate layer masking processes at 90nm and 65nm technology nodes. The empirical optical-and-process models can be same or different (such as with defocus) from the ones which are widely used in model based OPC and ORC. Similar to but different from conventional ORC, which normally addresses the minimum feature check or fatal error check, the model-based gate CD verification technique will focus on CD error prediction and CD error distribution analysis for gate CD related yield improvement efforts. Current commercial ORC or model-based verification tools provide the capability of EPE (edge placement error) check and analysis, and with certain additional techniques they may also provide the capability of gate CD prediction or simulation for selected targets or figures. The new model-based gate CD verification technique will provide the capability of full chip CD error prediction and CD error distribution analysis for all concerned small gate CD targets. INTROUCTIONFor low k1 lithography of advanced IC technology nodes at 90nm, 65nm and below, gate CD control is crucial to transistor functions and performances. While process variations, such as ACLV (across chip line-width variation), have been considered as the big contributors to gate CD variation and they can consume significant part of overall CD control budget, CD error budget for MBOPC (model based optical proximity/process correction), including model calibration and OPC correction, has been pushed to be as small as possible.With well-calibrated empirical OPC model, the main task of OPC correction is to fragment original layout edges in limited numbers and then move these fragments so that the EPE (edge placement errors) are minimized based on the optical-and-process model simulation. The various local specific features of the layout will have great impact on actual OPC fragmentation and OPC accuracy. In order to achieve the highest OPC accuracy, either OPC needs to be tuned and optimized for a specific layout design, or the layout design needs to be altered to cater for OPC limitations, which may need to go through a few cycles. For the both cases, model-based full chip CD error prediction has become inevitable OPC sign-off step or a feedback step in the close-looped design-to-silicon flows of 90nm and 65nm masking processes, especially for gate layers. In addition to these, model-based full chip CD error prediction would also be a necessary step if the amount or specific types of RET or OPC schemes need to be decided in the cases that RET & OPC accuracy, complexity, run-time and mask writing cost need to be analyzed and compromised.Put the above sequential steps and the feedback steps together, a simplifie...

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<title>Chip-level line-width prediction methodology</title>

Cited by 2 publications

References 0 publications

<title>Model-based OPC for sub-resolution assist feature enhanced layouts</title>

<title>Model-based OPC for sub-resolution assist feature enhanced layouts</title>

Full chip gate CD error prediction for model-based OPC

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