&lt;title&gt;Advanced space-qualified downlink image compression ASIC for commercial remote sensing applications&lt;/title&gt;

Brower, Bernard V.; Lan, Austin; Cosgrove, Michael A.; Lewis, D. H.; VanLare, Glenn R.

doi:10.1117/12.411555

Cited by 4 publications

(1 citation statement)

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“…It is the basis algorithm of the architecture presented in this thesis and will be presented in Section 2.4. 16 Embedded Zerotree of Wavelet transforms (EZW) 17 Set Partitioning In Hierarchical Trees (SPIHT) 18 set partitioned embedded block coder (SPECK) 19 Wavelet Difference Reduction (WDR) 20 Adaptively Scanned Wavelet Difference Reduction (ASWDR) 21 It is actually not explained in the source, what this abbreviation means. …”

Section: Icermentioning

confidence: 99%

Reconfigurable architecture for real-time image compression on-board satellites

Manthey

Krutz

Juurlink

2015

J. Appl. Remote Sens

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Data products of optical remote sensing systems are increasingly used in many areas of our everyday life. The spatial as well as the spectral resolution of satellite image data increases steadily with new missions resulting in a higher precision of known procedures and new application scenarios. While the memory capacity requirements can still be fulfilled, the transmission capacity becomes increasingly problematic. Real-time transmission of high-resolution image data is currently not possible.This thesis presents a new image data compression architecture that can be used for current and future projects at the German Aerospace Center (DLR). The architecture has region-of-interest support and offers flexible access to the compressed data based on the CCSDS 122.0-B-1 image data compression standard. Region of interest (ROI) coding can be useful in scenarios where on-board classification, registration, or object or change detection algorithms are used. It is also useful to decrease the amount of data that must be transferred to the ground station. Modifications to the standard have been made to permit a change of compression parameters and the re-organization of the bit-stream after compression. An additional index of the compressed data is created, which makes it possible to locate individual parts of the bit-stream. On request, compressed and stored images can be re-assembled and transmitted according to the application's needs and as requested by the ground station.The requirements, the design of the architecture, and its implementation based on reconfigurable hardware are presented. The architecture was developed for a spacequalified Xilinx Virtex 5QV, where a single instance of the architecture is capable of compressing images at a rate of up to 200 Mpx /s (or 400 Mbyte /s for 16 bit images). It operates at a clock frequency of 100 MHz and processes two image pixels per clock cycle. A Xilinx Virtex-5QV enables thereby compressing images with a width of up to 4096 pixels without the use of external memory. Without external memory and additional interfaces, the power consumption of the architecture is about 5 W. The proposed architecture is one of the fastest implementations yet reported and sufficient for recent high-resolution systems. Investigations in the resource and power consumption, as well as the availability of external storage have shown that it should be possible to integrate the design directly on a focal plane.

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Section: Icermentioning

confidence: 99%