PLATED-WIRE memory systems, DRO and NDRO, have well-known potential for economy and speed1,s. Importan properties of plated-wire memories are simplified module construction, high-output signal, low digit-write current, and impedance levels that permit economical diode access schemes. Table I lists characteristics for the memory module used for the system to be described. plated wire and associated electronics that provide capa-This paper places emphasis on the properties of the bility for high-speed interlace of conventional read-write (DRO) and read-only (NDRO) with fast write. The cylindrical one micron film memory cell structure is shown in Figure 1. The memory element has two cells per stored bit, defined by the orthogonal crossing of the two plated wire digit-sense lines by a word line. The geometrical symmetry of this structure permits effectwe access noise cancellation. This technology is restructive read-only capability are provided with non-uniquely versatile since both high-speed write and nonread-only (NDRO) sense signal amplitude as a function variable write and read electronics. Figure 2 shows of the amplitude of triangular word current pulses as well as destructive Read (DRO) signals. The plated wire response can be exploited for higher speed by switching word current mode a t logic speed. Figure 3 shows the word current waveforms for NDRO, WRITE and READ-WRITE. The Read-Write word current is nominally 900 mA, 75-ns duration with 20 ns rise and 15 ns fall. The Write-Only word current is 900 mA, 35 ns duration, no dwell a t peak. The NDRO word current is 400 mA, 10 ns rise, 10 1 1 s fall, no dwell at peak. Word current tlming jitter is held to about 2-4 ns, with a common word current control. The precise, multi-state word current control is generated at the full repetition rate in the following manner. The word line loop is connected (Figure 4) to a fixed voltage source through a charge storage diode conducting in the reverse direction; thus the voltage source impedance is very low and it switches to a high impedance as the diode is depleted of charge. For the case of trapezoidal word current waveform, useful for a read followed by a write, the initial linear word current rise is obtained similarly with the same .charge storage diode. For realizing the transistor switch. By applying command pulses, the dwell, the peak current is held clamped with anofher mode of operation can be controlled in an arbitrarily interlaced manner. Figure 5 presents sense Signals from such a high-speed interlaced word current mode OPeration. Figure 6 shows the store systems block diagram. Word selection is accomplished with one diode per word line -Main Computer Memory Utilizing Plated-Wire Elements", 1 McCallister, J. P., and Chong, C. F., "A 500 Nanosecond FPCCC, p. 305-31$' 1966.
