Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks

Abstract

The multiplicative depth of a logic network over the gate basis {∧, ⊕, ¬} is the largest number of ∧ gates on any path from a primary input to a primary output in the network. We describe a dynamic programming based logic synthesis algorithm to reduce the multiplicative depth in logic networks. It makes use of cut enumeration, tree balancing, and exclusive sum-of-products (ESOP) representations. Our algorithm has applications to cryptography and quantum computing, as a reduction in the multiplicative depth directly translates to a lower T -depth of the corresponding quantum circuit. Our experimental results show improvements in T -depth over state-of-the-art methods and over several hand-optimized quantum circuits for instances of AES, SHA, and floating-point arithmetic.

Synthesizing efficient circuits for Hamiltonian simulation

“…So depending upon the applications or other hardware constraints, one can design algorithms that optimize or reduce the count/depth of one particular type of quantum gate or other resources. For example, there are algorithms that does T-count and T-depth-optimal synthesis [26,27,28] given a unitary or does re-synthesis of a given circuit with reduced T-count, T-depth [29,30,31] or CNOT-count [32,33,34]. The non-Clifford T gate has known constructions in most of the error correction schemes and the cost of fault-tolerantly implementing it exceeds the cost of the Clifford group gates by as much as a factor of hundred or more [35,36,37].…”