Low-voltage PVT-insensitive bulk-driven OTA with enhanced DC gain in 65-nm CMOS process

Veldandi, Harikrishna; Ahamed, Shaik Rafi

doi:10.1016/j.aeue.2018.03.033

Cited by 19 publications

(13 citation statements)

References 30 publications

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“…The gain ( ) of the differential GD nMOSFETs pair input stage is determined by using ( 4): (4) where is the transconductance value of transistor M1, and are the channel conductance values of transistors M7 and M9, respectively.…”

Section: Very Lvs Cmos Gd Op-amp Descriptionmentioning

confidence: 99%

“…In recent years, the growing global electronics markets' needs for portable, wearable, wireless, battery-driven, and reliable electronics in submicron and nanometer VLSI analog and mixed-signal systems have generated the desire and opened new horizons in the field of scientific researches to design very lowvoltages (LVs) power supplies and efficient low power (LP) complementary metal-oxide field-effect transistors (CMOSFETs) based analog sub-circuits [1][2][3]. In those systems, the threshold voltages ( ) of the MOSFETs are not reducing compared to the rate at which the power supplies voltages reduction [4] and the ratio of lengths-to-widths of the down-scaled MOSFETs channels [5]. In very LVs power supplies and LP MOSFETs circuits, the minimum power supplies voltages must be equal to or greater than the values, and this imposes an additional strict restriction on the possibility of reducing the power supplies voltages [6].…”

Section: Introductionmentioning

confidence: 99%

“…However, Digital MOSFETs circuits benefit from the use of low-values MOSFETs and very LVs power supplies to improve their performance specifications. Whereas, the use of low-values MOSFETs and very LVs power supplies lead to the deterioration in the performance specifications of the analog MOSFETs circuits due to the effects of gate leakage currents, short-channel lengths, and permissible noise voltages margins [4][5][6][7][8][9]. Consequently, these effects increase the complexity of designing the analog…”

Section: Introductionmentioning

confidence: 99%

“…To overcome these shortcomings, several promising very LVs power supplies' design techniques have introduced to increase the and values of the very LVs power supplies and highperformance specifications CMOS Op-Amp circuits topologies. Among these design techniques, the most widely used are: parallel-connected nMOSFETs and pMOSFETs differential input pairs [15,16], DC levelshifters MOSFETs [16][17][18][19][20], self-cascoded MOSFETs [17,19], sub-region operation MOSFETs [17,19], dynamic MOSFETs [19], floating-gate (FG) MOSFETs [17][18][19][20][21], quasi floating-gate (QFG) MOSFETs [18,20,22,23], and bulk-driven (BD) MOSFETs [4,[17][18][19]. There are advantages and disadvantages to each of these very LVs power supplies' design techniques reported in [4,[15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

AL-Qaysi

Jasim

Hameed

2020

IJEECS

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

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Section: Very Lvs Cmos Gd Op-amp Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

AL-Qaysi

Jasim

Hameed

2020

IJEECS

View full text Add to dashboard Cite

show abstract

“…Many active components were designed with this technique, including operational amplifiers [8], OTAs [9], differential amplifiers [10], current mirrors [11], and current conveyors [12]. Using a BD input stage is another way to achieve LV and LP operation [13][14][15][16][17]. For conventional MOS transistors, the gate terminal receives the input signal, while the bulk terminal is connected to either the highest or lowest power rails, depending on whether the transistor is PMOS or NMOS.…”

Section: Introductionmentioning

confidence: 99%

Bulk-driven current conveyor optimization using simulation-based method

2022

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This paper presents the optimization of a novel low-voltage (LV) and low-power (LP) bulk driven current conveyor (CCII). For the bulk-driven circuits, the transistors are biased at the subthreshold regime for LV and LP operation. In contrast, the input transistors of the differential stage are controlled from the bulk terminals to achieve a rail-to-rail input voltage range. A simulation-based technique is adapted for the optimal design of LV-LP bulk driven CCII, using the single-objective particle swarm optimization (PSO) algorithm. It is designed using CMOS 0.18 μm technology to operate at a voltage of 0.3 V and have a power consumption of 37 nW. Optimization results and also process/temperature corner results confirm the correct operation of the designed circuit.

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A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process

Hosseinnejad

Katebi

Erfanian

et al. 2022

Circuit Theory & Apps

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This paper presents a programmable neurostimulator 4 Â V DD with 7.2 V operating voltage in a 0.18-μm/1.8 V CMOS process. The output voltage compliance exceeds 6.2 V. A current gain control is designed to adjust bias current.A 5-bit current mode digital-to-analog converter (DAC) is used to set delivered current in current driver. A high output impedance current mirror is designed to guarantee charge balancing. The charge mismatch after biphasic stimulation is about 0.14%. Moreover, current mirrors are turned off after stimulation to decrease power consumption. The headroom voltage is about 1 V for all the voltage drivers and the current mirrors. The proposed neurostimulator occupies 0.95 Â 0.95 mm 2 with a maximum current range of 0-2000 μA and a power consumption less than 60 μW.

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Low-voltage PVT-insensitive bulk-driven OTA with enhanced DC gain in 65-nm CMOS process

Cited by 19 publications

References 30 publications

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

Bulk-driven current conveyor optimization using simulation-based method

A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process

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