Low-voltage MOS Current Mode Logic for Low-Power and High Speed Applications

Wu, Yangbo; Hu, Jianping

doi:10.3923/itj.2011.2470.2475

Cited by 14 publications

(15 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, the power consumption of a MCML gate is constant in spite of its operating frequencies and activities of input signals [9,10]. This means that the static power consumption of MCML cells is significantly higher than equivalent implementations using conventional static CMOS logic [11,12].…”

Section: Introductionmentioning

confidence: 87%

Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors

Cao¹,

Hu²,

Xue-Cheng³

2014

TOAUTOCJ

Self Cite

View full text Add to dashboard Cite

Abstract:In this paper, a power-gating technology for single-rail MOS Current Mode Logic (SRMCML) circuits is presented, which use the high-threshold PMOS transistors as linear load resistors to reduce the power dissipation in the sleep mode. The basic SRMCML cells, such as buffer/inverter, AND2/NAND2, AND3/NAND3, OR2/NOR2, OR3/NOR3, XOR2/XNOR2, multiplexer, and 1-bit full adder, are used to verify the effectiveness of the proposed power-gating scheme. The equivalent model for calculating energy dissipations of the power-gating SRMCML circuits is constructed. All circuits are simulated with HSPICE at a 130 nm CMOS process. By simulating power-gating SRMCML circuits in active and sleep modes, it is concluded that the power dissipation of power-gating SRMCML circuits in sleep mode is reduced with the decrease of the device sizes of high-threshold PMOS sleep transistors, while the power dissipation of power-gating SRMCML circuits is almost independent of the device sizes of sleep transistors in active mode. The power dissipation comparisons among power-gating SRMCML, conventional SRMCML, and power-gating static CMOS circuits are carried out. The power dissipation of the proposed power-gating SRMCML circuits is the least among the three above mentioned structures.

show abstract

Section: Introductionmentioning

confidence: 87%

Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors

Cao¹,

Hu²,

Xue-Cheng³

2014

TOAUTOCJ

Self Cite

View full text Add to dashboard Cite

show abstract

“…The power dissipation of MCML circuits is not related to operating frequencies, and thus the power consumption of MCML circuits is lower than the conventional CMOS ones in high speed applications [7,8]. However, this feature also leads to a disadvantage that the power consuming of MCML circuits is much larger than the static CMOS ones for lowfrequency operating [9].…”

Section: Introductionmentioning

confidence: 99%

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Geng¹,

Hu²,

Zou³

2014

TOEEJ

Self Cite

View full text Add to dashboard Cite

Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.

show abstract

“…Moreover, For the OR/NOR logic cell, the proposed SRMCML can avoid the devices in series configuration, since the logic evaluation block of the SRMCML OR/NOR logic cell can been realized by only using MOS transistors in parallel. This can further reduce power dissipations because of the low source voltage [13].…”

Section: Introductionmentioning

confidence: 99%

Single-Rail MOS Current Mode Logic Circuits for Low-Power and High-Speed Applications

Li¹,

Cao²,

Hu³

2012

AISS

View full text Add to dashboard Cite

MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, almost all MCML circuits are realized with dual-rail scheme. The dual-rail logic circuits increase extra area overhead and the complexity of the layout place and route. Moreover, little standard cells of the dualrail logic circuits have been developed for place-and-route tools, such as Cadence Encounter. In this paper, a single-rail scheme of MCML circuits is proposed. The design methods of the basic single-rail MOS Current-Mode Logic (SRMCML) circuits are presented, such as inverter/buffer, OR2/NOR2, AND2/NAND2, OR3/NOR3, and 1-bit full adder. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process. The power dissipations of the basic SRMCML cells are compared with the conventional dual-rail MCML ones. The power dissipation of the proposed SDMCML circuits is almost the same as the conventional dual-rail ones. The SRMCML circuit can attain smaller powerdelay product than dual-rail MCML ones because of its single-rail scheme.

show abstract

Low-voltage MOS Current Mode Logic for Low-Power and High Speed Applications

Cited by 14 publications

References 6 publications

Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors

Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Single-Rail MOS Current Mode Logic Circuits for Low-Power and High-Speed Applications

Contact Info

Product

Resources

About