Abstract:Application of conducting ferroelectric domain walls (DW) as functional elements may facilitate development of conceptually new resistive switching devices. In a conventional approach, several orders of magnitude change in resistance can be achieved by controlling the DWs density using super-coercive voltage. However, a deleterious characteristic of this approach is high-energy cost of polarization reversal due to high leakage current. Here, we demonstrate a new approach based on tuning the conductivity of DWs… Show more
“…[13][14][15][16][17] However, till now, only HZO-based gate stack 2D NC-FETs can obtain ultralow SS (<10 mV dec −1 ) and quasi-free hysteresis simultaneously. [14] As a ferroelectric materials system with excellent ferroelectric and electro-optic properties, single crystal LiNbO 3 (LNO) has attracted huge attention, [25][26][27][28] which shows the largest spontaneous polarization (50-80 µC cm −2 ) and possesses unique ferroelectric domains direction with only the +c and the −c. Recently, owing to full-fledged preparation of high-quality single crystal LNO thin film by ion-implanted method, the CMOS-compatible LNO integrated system is realized and becomes a promising candidate for future electronic and optical integrated chips.…”
Power consumption is one of the most challenging bottlenecks for complementary metal‐oxide–semiconductor integration. Negative‐capacitance field‐effect transistors (NC‐FETs) offer a promising platform to break the thermionic limit defined by the Boltzmann tyranny and architect energy‐efficient devices. However, it is a great challenge to achieving ultralow‐subthreshold‐swing (SS) (10 mV dec−1) and small‐hysteresis NC‐FETs simultaneously at room temperature, which has only been reported using the hafnium zirconium oxide system. Here, based on a ferroelectric LiNbO3 thin film with great spontaneous polarization, an ultralow‐SS NC‐FET with small hysteresis is designed. The LiNbO3 NC‐FET platform exhibits a record‐low SS of 4.97 mV dec−1 with great repeatability due to the superior capacitance matching characteristic as evidenced by the negative differential resistance phenomenon. By modulating the structure and operating parameters (such as channel length (Lch), drain–sourse bias (Vds), and gate bias (Vg)) of devices, an optimized SS from ≈40 to ≈10 mV dec−1 and hysteresis from ≈900 to ≈60 mV are achieved simultaneously. The results provide a new potential method for future highly integrated electronic and optical integrated energy‐efficient devices.
“…[13][14][15][16][17] However, till now, only HZO-based gate stack 2D NC-FETs can obtain ultralow SS (<10 mV dec −1 ) and quasi-free hysteresis simultaneously. [14] As a ferroelectric materials system with excellent ferroelectric and electro-optic properties, single crystal LiNbO 3 (LNO) has attracted huge attention, [25][26][27][28] which shows the largest spontaneous polarization (50-80 µC cm −2 ) and possesses unique ferroelectric domains direction with only the +c and the −c. Recently, owing to full-fledged preparation of high-quality single crystal LNO thin film by ion-implanted method, the CMOS-compatible LNO integrated system is realized and becomes a promising candidate for future electronic and optical integrated chips.…”
Power consumption is one of the most challenging bottlenecks for complementary metal‐oxide–semiconductor integration. Negative‐capacitance field‐effect transistors (NC‐FETs) offer a promising platform to break the thermionic limit defined by the Boltzmann tyranny and architect energy‐efficient devices. However, it is a great challenge to achieving ultralow‐subthreshold‐swing (SS) (10 mV dec−1) and small‐hysteresis NC‐FETs simultaneously at room temperature, which has only been reported using the hafnium zirconium oxide system. Here, based on a ferroelectric LiNbO3 thin film with great spontaneous polarization, an ultralow‐SS NC‐FET with small hysteresis is designed. The LiNbO3 NC‐FET platform exhibits a record‐low SS of 4.97 mV dec−1 with great repeatability due to the superior capacitance matching characteristic as evidenced by the negative differential resistance phenomenon. By modulating the structure and operating parameters (such as channel length (Lch), drain–sourse bias (Vds), and gate bias (Vg)) of devices, an optimized SS from ≈40 to ≈10 mV dec−1 and hysteresis from ≈900 to ≈60 mV are achieved simultaneously. The results provide a new potential method for future highly integrated electronic and optical integrated energy‐efficient devices.
“…The possibilities afforded by controllable "now-you-see-it-now you-don't" mercurial conducting domain wall conduits for new kinds of devices were noted in Siedel et al's seminal work [6], where a proof-of-concept memristor was even explicitly demonstrated: conduction states were varied by writing different numbers of domain wall channels between source and drain electrodes using a conducting AFM tip. More operationally pragmatic domain wall memristors [33][34][35][36], transistors [37] and binary memory bits [38,39] have since been developed and their potential applications are growing (in neuromorphic circuitry, for example).…”
This "perspectives" article briefly summarises what is known about electrically conducting domain walls. It highlights insights into the underlying causes of enhanced current transport, developed despite the frustrations and limitations of the standard two-probe source and drain measurements that have dominated the field to date (because of the pervasive use of conventional conducting Atomic Force Microscopy). The article gives a feel for the unique possibilities offered by conducting domain walls, in future forms of agile electronics. Indeed, it is imagined that domain walls and domain wall junctions might eventually allow for entire nanoscale circuits (devices and their interconnects) to be created in one instant, for one purpose, only to be wiped clean and rewritten in a different form, for a different purpose, in the next instant. Malleable domain wall network architecture, that can continually metamorphose, could represent a kind of technological genie, granting wishes on demand for radical moment-to-moment changes in electronic function.
“…Additionally, through electrical control of the wall length, [ 24 ] wall charge state/conformation, [ 136,137 ] and density, [ 138 ] multi‐level states or the ‘memristor device’ promising much higher storage densities than what can be achieved with just binary logic were demonstrated. In fact, by varying the magnitude of applied electrical pulses, the domain wall density in a two‐terminal capacitor was tuned to achieve ≈100 different states (within two orders of magnitude change in resistance).…”
Ferroelectric domain walls naturally form at nanoscale interfaces of polar order leading to electronic properties distinct from the bulk that can also be electrically programmed. These nanoscale features currently are being actively explored for the development of agile, low‐energy electronics for applications in memory, logic, and brain‐inspired neuromorphic computing. In this article, the authors review the state of the art, the latest developments, and outline key device and material challenges, emerging opportunities, and new directions for the accelerated engineering and commercialization of domain wall technology.
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